Datasheet > FM25V40-DCG

FM25V40-DCG

更新时间： 2022-02-26 11:02:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
23页	851K
描述
4-Mbit (512 K Ã 8) Serial (SPI) F-RAM

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数据手册

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FM25V40-DCG 数据手册

PRELIMINARY

FM25V40

For a microcontroller that has no dedicated SPI bus, a

Serial Opcode

general-purpose port may be used. To reduce hardware

resources on the controller, it is possible to connect the two data

pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.

Figure 4 shows such a configuration, which uses only three pins.

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

FM25V40 uses the standard opcodes for memory accesses.

Invalid Opcode

Most Significant Bit (MSB)

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin until the

next falling edge of CS, and the SO pin remains tristated.

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data transmission.

Status Register

The 4-Mbit serial F-RAM requires a 3-byte address for any read

or write operation. Because the address is only 19 bits, the first

five bits, which are fed in are ignored by the device. Although

these five bits are ‘don’t care’, Cypress recommends that these

bits be set to 0s to enable seamless transition to higher memory

densities.

FM25V40 has an 8-bit Status Register. The bits in the Status

described in Table 3 on page 7.

Figure 3. System Configuration with SPI Port

SCK

MOSI

MISO

SCK

SI SO

SPI

Microcontroller

FM25V40

HOLD WP

C S 1

H O LD 1

W P 1

C S 2

H O LD 2

W P 2

Figure 4. System Configuration without SPI Port

P1.0

P1.1

SCK

SI SO

Microcontroller

FM25V40

HOLD WP

P1.2

active. If the clock starts from a HIGH state (in mode 3), the first

SPI Modes

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

FM25V40 may be driven by a microcontroller with its SPI

peripheral running in either of the following two modes:

The two SPI modes are shown in Figure 5 on page 6 and Figure

6 on page 6. The status of the clock when the bus master is not

transferring data is:

■ SPI Mode 0 (CPOL = 0, CPHA = 0)

■ SPI Mode 3 (CPOL = 1, CPHA = 1)

For both these modes, the input data is latched in on the rising

edge of SCK starting from the first rising edge after CS goes

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

Document Number: 001-87288 Rev. *A

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