Datasheet > FM25Q02

FM25Q02

更新时间： 2023-12-06 20:08:50

品牌	Logo	应用领域
复旦微 - FM		/
页数	文件大小	规格书
80页	1712K
描述
SPI NOR Flash

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FM25Q02 数据手册

6. Pin Descriptions

Serial Clock (CLK): The SPI Serial Clock Input (CLK) pin provides the timing for serial input and

output operations.

Serial Data Input, Output and I/Os (DI, DO and DQ₀, DQ₁, DQ₂, DQ₃): The FM25Q02 supports

standard SPI, Dual SPI, Quad SPI and QPI operation. Standard SPI instructions use the

unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the

rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO

(output) to read data or status from the device on the falling edge of CLK.

Dual/Quad SPI and QPI instructions use the bidirectional DQ pins to serially write instructions,

addresses or data to the device on the rising edge of CLK and read data or status from the

device on the falling edge of CLK. Quad SPI and QPI instructions require the non-volatile Quad

Enable bit (QE) in Status Register-2 to be set. When QE=1, the WP# pin becomes DQ₂and

HOLD# pin becomes DQ₃.

Chip Select (CS#): The SPI Chip Select (CS#) pin enables and disables device operation.

When CS# is high, the device is deselected and the Serial Data Output (DO, or DQ₀, DQ₁, DQ₂,

DQ₃) pins are at high impedance. When deselected, the devices power consumption will be at

standby levels unless an internal erase, program or write status register cycle is in progress.

When CS# is brought low, the device will be selected, power consumption will increase to active

levels and instructions can be written to and data read from the device. After power-up, CS#

must transition from high to low before a new instruction will be accepted. The CS# input must

track the VCC supply level at power-up (see “9Write Protection” and Figure 72). If needed a pull-

up resister on CS# can be used to accomplish this.

HOLD (HOLD#): The HOLD# pin allows the device to be paused while it is actively selected.

When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals

on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device

operation can resume. The HOLD# function can be useful when multiple devices are sharing the

same SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for

Quad I/O, the HOLD# pin function is not available since this pin is used for DQ₃.

Write Protect (WP#): The Write Protect (WP#) pin can be used to prevent the Status Registers

from being written. Used in conjunction with the Status Register’s Block Protect (CMP, TB, BP2,

BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or

the entire memory array can be hardware protected. The WP# pin is active low. However, when

the QE bit of Status Register-2 is set for Quad I/O, the WP# pin function is not available since

this pin is used for DQ₂.

Datasheet

FM25Q022M-BITSERIAL FLASH MEMORY

Ver. 1.4

1 2 3 456 7 8...80

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