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Datasheet > FM25C160UEM8
FM25C160UEM8 PDF预览

FM25C160UEM8

更新时间： 2024-01-10 06:22:35
品牌 Logo 应用领域
其他 - ETC 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
11页 103K
描述
SPI Serial EEPROM

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中文翻译

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FM25C160UEM8 技术参数

生命周期：Contact Manufacturer包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.32.00.51
风险等级：5.73最大时钟频率 (fCLK)：2.1 MHz
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.9 mm内存密度：16384 bit
内存集成电路类型：EEPROM内存宽度：8
功能数量：1端子数量：8
字数：2048 words字数代码：2000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2KX8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：SERIAL座面最大高度：1.75 mm
串行总线类型：SPI最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：3.9 mm
最长写入周期时间 (tWC)：10 msBase Number Matches：1

FM25C160UEM8 数据手册

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Pin Description  
Functional Description  
The Serial Peripheral Interface (SPI) of FM25C160U consists of  
an 8-bit Instruction register to decode a specific instruction to be  
executed. Six different instructions (Opcodes) are incorporated  
on FM25C160U for various operations. Table2 lists the instruc-  
tions set and the format for proper operation. All Opcodes, Array  
addresses and Data are transferred in “MSB first-LSB last”  
fashion. Detailed information is provided under individual instruc-  
tion descriptions.  
Chip Select (/CS)  
This is an active low input pin to the EEPROM and is generated by  
a master that is controlling the EEPROM. A low level on this pin  
selects the EEPROM and a high level deselects the EEPROM. All  
serial communications with the EEPROM is enabled only when  
this pin is held low.  
Serial Clock (SCK)  
TABLE 2. Instruction Set  
ThisisaninputpintotheEEPROMandisgeneratedbythemaster  
that is controlling the EEPROM. This is a clock signal that  
synchronizes the communication between a master and the  
EEPROM. All input information (SI) to the EEPROM is latched on  
the rising edge of this clock input, while output data (SO) from the  
EEPROM is driven after the falling edge of this clock input.  
Instruction Instruction  
Operation  
Name  
WREN  
WRDI  
Opcode  
00000110  
00000100  
00000101  
00000001  
00000011  
Write Enabled  
Write Disabled  
Serial Input (SI)  
RDSR  
WRSR  
READ  
Read Status Register  
Write Status Register  
ThisisaninputpintotheEEPROMandisgeneratedbythemaster  
that is controlling the EEPROM. The master transfers Input  
information (Instruction Opcodes, Array addresses and Data)  
serially via this pin into the EEPROM. This Input information is  
latched on the rising edge of the SCK.  
Read Data from Memory  
Array  
WRITE  
00000010  
Write Data to Memory Array  
Serial Output (SO)  
In addition to the Instruction register, FM25C160U also contains  
an8-bitStatusregisterthatcanbeaccessedbyRDSRandWRSR  
instructions. Only the least significant (LSB) 4 bits are defined at  
present and the most significant (MSB) 4 bits are undefined (don’t  
care).TheLSB4bitsdefineBlockWriteProtectionlevels(BP1and  
BP0), Write-enable status (WEN) and Busy/Rdy status (/RDY) of  
the EEPROM. Table 3 illustrates the format:  
This is an output pin from the EEPROM and is used to transfer  
Output data via this pin to the controlling master. Output data is  
serially shifted out on this pin after the falling edge of the SCK.  
Hold (/HOLD)  
This is an active low input pin to the EEPROM and is generated by  
the master that is controlling the EEPROM. When driven low, this  
pin suspends any current communication with the EEPROM. The  
suspended communication can be resumed by driving this pin  
high. This feature eliminates the need to re-transmit the entire  
sequence by allowing the master to resume the communication  
from where it was left off. This pin should be tied high if this feature  
is not used. Refer Hold Function description for additional  
details.  
TABLE 3. Status Register Format  
Bit  
7
Bit  
6
Bit  
5
Bit  
4
Bit  
3
Bit  
2
Bit  
1
Bit  
0
X
X
X
X
BP1  
BP0 WEN RDY  
Refer RDSR and WRSR instruction descriptions for additional  
information on Status register operations.  
Write Protect (/WP)  
This is an active low input pin to the EEPROM. This pin allows  
enabling and disabling of writes to memory array and status  
register of the EEPROM. When this pin is held low, writes to the  
memory array and status register are disabled. When this pin is  
held high, writes to the memory array and status register are  
enabled. Status of this pin does not affect operations other than  
array write and status register write. /WP signal going low at any  
time will inhibit programming, except when an internal write has  
already begun. If an internal write cycle has already begun, /WP  
signal going low will have no effect on the write. Refer Table1 for  
Write Protection matrix.  
Table1. Write Protection Matrix  
Protected Blocks  
/WP Pin  
Low  
WEN Bit  
Status Register  
Write Protected  
Write Protected  
Write Allowed  
(by BP1-BP0)  
Write Protected  
Write Protected  
Write Protected  
Unprotected Blocks  
Write Protected  
X
0
1
High  
Write Protected  
High  
Write Allowed  
6
www.fairchildsemi.com  
FM25C160U Rev. A  
1...3456789...11

中文翻译

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