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FM25C160B-GA PDF预览

FM25C160B-GA

更新时间: 2024-01-23 16:23:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
20页 716K
描述
Memory Circuit, 2KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8

FM25C160B-GA 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:unknownHTS代码:8542.32.00.71
风险等级:5.76JESD-30 代码:R-PDSO-G8
长度:4.9 mm内存密度:16384 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:8
湿度敏感等级:1功能数量:1
端子数量:8字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:125 °C最低工作温度:-40 °C
组织:2KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm

FM25C160B-GA 数据手册

 浏览型号FM25C160B-GA的Datasheet PDF文件第3页浏览型号FM25C160B-GA的Datasheet PDF文件第4页浏览型号FM25C160B-GA的Datasheet PDF文件第5页浏览型号FM25C160B-GA的Datasheet PDF文件第7页浏览型号FM25C160B-GA的Datasheet PDF文件第8页浏览型号FM25C160B-GA的Datasheet PDF文件第9页 
FM25C160B  
SPI Modes  
Table 1. Opcode commands  
Name Description  
WREN  
FM25C160B may be driven by a microcontroller with its SPI  
peripheral running in either of the following two modes:  
Opcode  
0000 0110b  
0000 0100b  
0000 0101b  
0000 0001b  
0000 0011b  
0000 0010b  
Set write enable latch  
Write disable  
SPI Mode 0 (CPOL = 0, CPHA = 0)  
SPI Mode 3 (CPOL = 1, CPHA = 1)  
WRDI  
RDSR  
WRSR  
READ  
WRITE  
Read Status Register  
Write Status Register  
Read memory data  
Write memory data  
For both these modes, the input data is latched in on the rising  
edge of SCK starting from the first rising edge after CS goes  
active. If the clock starts from a HIGH state (in mode 3), the first  
rising edge after the clock toggles is considered. The output data  
is available on the falling edge of SCK.  
WREN - Set Write Enable Latch  
The two SPI modes are shown in Figure 4 on page 6 and Figure  
5 on page 6. The status of the clock when the bus master is not  
transferring data is:  
The FM25C160B will power up with writes disabled. The WREN  
command must be issued before any write operation. Sending  
the WREN opcode allows the user to issue subsequent opcodes  
for write operations. These include writing the Status Register  
(WRSR) and writing the memory (WRITE).  
SCK remains at 0 for Mode 0  
SCK remains at 1 for Mode 3  
Sending the WREN opcode causes the internal Write Enable  
Latch to be set. A flag bit in the Status Register, called WEL,  
indicates the state of the latch. WEL = ‘1’ indicates that writes are  
permitted. Attempting to write the WEL bit in the Status Register  
has no effect on the state of this bit – only the WREN opcode can  
set this bit. The WEL bit will be automatically cleared on the rising  
edge of CS following a WRDI, a WRSR, or a WRITE operation.  
This prevents further writes to the Status Register or the F-RAM  
array without another WREN command. Figure 6 illustrates the  
WREN command bus configuration.  
The device detects the SPI mode from the status of the SCK pin  
when the device is selected by bringing the CS pin LOW. If the  
SCK pin is LOW when the device is selected, SPI Mode 0 is  
assumed and if the SCK pin is HIGH, it works in SPI Mode 3.  
Figure 4. SPI Mode 0  
CS  
0
1
2
3
4
5
6
7
SCK  
SI  
Figure 6. WREN Bus Configuration  
CS  
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
MSB  
LSB  
SCK  
SI  
0
0
0
0
0
1
1
0
Figure 5. SPI Mode 3  
HI-Z  
SO  
CS  
WRDI - Reset Write Enable Latch  
0
1
2
3
4
5
6
7
The WRDI command disables all write activity by clearing the  
Write Enable Latch. The user can verify that writes are disabled  
by reading the WEL bit in the Status Register and verifying that  
WEL is equal to ‘0’. Figure 7 illustrates the WRDI command bus  
configuration.  
SCK  
SI  
7
6
5
4
3
2
1
0
MSB  
LSB  
Figure 7. WRDI Bus Configuration  
Power Up to First Access  
CS  
The FM25C160B is not accessible for a tPU time after power up.  
Users must comply with the timing parameter tPU, which is the  
minimum time from VDD (min) to the first CS LOW.  
0
1
2
3
4
5
6
7
SCK  
SI  
Command Structure  
0
0
0
0
0
0
1
0
There are six commands, called opcodes, that can be issued by  
the bus master to the FM25C160B. They are listed in Table 1.  
These opcodes control the functions performed by the memory.  
HI-Z  
SO  
Document Number: 001-86150 Rev. *C  
Page 6 of 20  
 
 
 
 

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