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FM24CL04-GTR PDF预览

FM24CL04-GTR

更新时间: 2024-01-08 03:10:07
品牌 Logo 应用领域
铁电 - RAMTRON 光电二极管内存集成电路
页数 文件大小 规格书
12页 280K
描述
Memory Circuit, 512X8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8

FM24CL04-GTR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:unknownHTS代码:8542.32.00.71
风险等级:5.14JESD-30 代码:R-PDSO-G8
长度:4.9 mm内存密度:4096 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:8
功能数量:1端子数量:8
字数:512 words字数代码:512
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512X8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):3.65 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

FM24CL04-GTR 数据手册

 浏览型号FM24CL04-GTR的Datasheet PDF文件第1页浏览型号FM24CL04-GTR的Datasheet PDF文件第3页浏览型号FM24CL04-GTR的Datasheet PDF文件第4页浏览型号FM24CL04-GTR的Datasheet PDF文件第5页浏览型号FM24CL04-GTR的Datasheet PDF文件第6页浏览型号FM24CL04-GTR的Datasheet PDF文件第7页 
FM24CL04  
Address  
Latch  
128 x 32  
FRAM Array  
Counter  
8
Serial to Parallel  
Converter  
SDA  
SCL  
Data Latch  
WP  
A1  
Control Logic  
A2  
Figure 1. Block Diagram  
Pin Description  
Pin Name  
I/O  
Pin Description  
A1-A2  
Input  
Address 1-2: The address pins set the device select address. The device address value  
in the 2-wire slave address must match the setting of these two pins. These pins are  
internally pulled down.  
SDA  
I/O  
Serial Data/Address: This is a bi-directional pin used to shift serial data and addresses  
for the two-wire interface. It employs an open-drain output and is intended to be wire-  
OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt  
trigger for noise immunity and the output driver includes slope control for falling  
edges. A pull-up resistor is required.  
SCL  
WP  
Input  
Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of  
the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL  
input also incorporates a Schmitt trigger input for improved noise immunity.  
Write Protect: When WP is high, the entire array is write-protected. When WP is low,  
all addresses may be written. This pin is internally pulled down.  
Input  
-
NC  
VDD  
VSS  
No connect  
Supply Supply Voltage  
Supply Ground  
Rev. 3.2  
Feb. 2011  
Page 2 of 12  

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