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FIN3385

更新时间: 2024-09-30 22:40:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 显示器
页数 文件大小 规格书
9页 284K
描述
Low Voltage 28-Bit Flat Panel Display Link Serializers

FIN3385 数据手册

 浏览型号FIN3385的Datasheet PDF文件第2页浏览型号FIN3385的Datasheet PDF文件第3页浏览型号FIN3385的Datasheet PDF文件第4页浏览型号FIN3385的Datasheet PDF文件第5页浏览型号FIN3385的Datasheet PDF文件第6页浏览型号FIN3385的Datasheet PDF文件第7页 
October 2003  
Revised January 2004  
FIN3385 FIN3383  
Low Voltage 28-Bit Flat Panel Display Link Serializers  
General Description  
Features  
The FIN3385 and FIN3383 transform 28 bit wide parallel  
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low  
Voltage Differential Signaling) data streams. A phase-  
locked transmit clock is transmitted in parallel with the data  
steam over a separate LVDS link. Every cycle of transmit  
clock 28 bits of input LVTTL data are sampled and trans-  
mitted.  
Low power consumption  
20 MHz to 85 MHz shift clock support  
±1V common-mode range around 1.2V  
Narrow bus reduces cable size and cost  
High throughput (up to 2.38 Gbps throughput)  
Internal PLL with no external component  
Compatible with TIA/EIA-644 specification  
These chipsets are an ideal solution to solve EMI and  
cable size problems associated with wide and high-speed  
TTL interfaces.  
Devices are offered in 48- and 56-lead TSSOP  
packages  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN3383MTD  
FIN3385MTD  
MTD56  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
TABLE 1. Display Panel Link Serializers/De-Serializers Chip Matrix  
Part  
CLK Frequency LVTTL IN  
LVDS OUT  
Package  
56 TSSOP  
56 TSSOP  
FIN3385  
FIN3383  
85  
66  
28  
28  
4
4
Block Diagram  
Functional Diagram for FIN3385 and FIN3383  
© 2004 Fairchild Semiconductor Corporation  
DS500864  
www.fairchildsemi.com  

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