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FIN3366MTDX

更新时间： 2024-10-01 14:50:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管接口集成电路
页数 文件大小 规格书
19页 771K
描述
Line Receiver, 3 Func, 3 Rcvr, PDSO48, 6.10 MM, MO-153, TSSOP-48

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FIN3366MTDX 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP48,.3,20针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G48
长度：14 mm功能数量：3
端子数量：48最高工作温度：70 °C
最低工作温度：-10 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：3.3 V认证状态：Not Qualified
最大接收延迟：接收器位数：3
座面最大高度：1.1 mm子类别：Line Driver or Receivers
最大压摆率：135 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：6.1 mm
Base Number Matches：1

FIN3366MTDX 数据手册

 浏览型号FIN3366MTDX的Datasheet PDF文件第2页浏览型号FIN3366MTDX的Datasheet PDF文件第3页浏览型号FIN3366MTDX的Datasheet PDF文件第4页浏览型号FIN3366MTDX的Datasheet PDF文件第5页浏览型号FIN3366MTDX的Datasheet PDF文件第6页浏览型号FIN3366MTDX的Datasheet PDF文件第7页 
June 2003  
Revised August 2003  
FIN3385 • FIN3386,  
FIN3383 • FIN3384,  
FIN3365 • FIN3366,  
FIN3363 • FIN3364  
Low Voltage 24/18 Bit Flat Panel Display Link  
Serializers/De-Serializers  
General Description  
Features  
■ Low power consumption  
The FIN3385/FIN3383/FIN3365/FIN3363 transforms 28/21  
bit wide parallel LVTTL (Low Voltage TTL) data into 4/3  
serial LVDS (Low Voltage Differential Signaling) data  
streams. A phase-locked transmit clock is transmitted in  
parallel with the data steam over a separate LVDS link.  
Every cycle of transmit clock 28/21 bits of input LVTTL data  
are sampled and transmitted.  
■ 20 MHz to 85 MHz shift clock support  
■ 50% duty cycle on the clock output of receiver  
■ ±1V common-mode range around 1.2V  
■ Narrow bus reduces cable size and cost  
■ High throughput (up to 2.38 Gbps throughput)  
■ Internal PLL with no external component  
■ Compatible with TIA/EIA-644 specification  
The FIN3386/FIN3384/FIN3366/FIN3364 receives and  
converts the 4/3 serial LVDS data streams back into 28/21  
bits of LVTTL data. Refer to Table 1 for a matrix summary  
of the Serializers and De-serializers available. For the  
FIN3385, at a transmit clock frequency of 85 MHz, 28 bits  
of LVTTL data are transmitted at a rate of 595 Mbps per  
LVDS channel.  
■ Devices are offered in 48- and 56-lead TSSOP  
packages  
These chipsets are an ideal solution to solve EMI and  
cable size problems associated with wide and high-speed  
TTL interfaces.  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN3363MTD  
(Preliminary)  
MTD48  
MTD48  
MTD48  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
FIN3364MTD  
(Preliminary)  
FIN3365MTD  
(Preliminary)  
FIN3366MTD  
(Preliminary)  
FIN3383MTD  
MTD56  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
FIN3384MTD  
(Preliminary)  
FIN3385MTD  
MTD56  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
FIN3386MTD  
(Preliminary)  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
© 2003 Fairchild Semiconductor Corporation  
DS500864  
www.fairchildsemi.com  
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