Datasheet > FDMF6820B

FDMF6820B

更新时间： 2024-02-25 06:34:16

品牌	Logo	应用领域
安森美 - ONSEMI		服务器主板节能技术驱动接口集成电路
页数	文件大小	规格书
21页	927K
描述
超小型、高性能、高频DrMOS模块

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技术参数
数据手册

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FDMF6820B 技术参数

是否无铅：	不含铅	生命周期：	Active
包装说明：	PQFN-40	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
Factory Lead Time：	16 weeks	风险等级：	5.66
接口集成电路类型：	HALF BRIDGE BASED MOSFET DRIVER	JESD-609代码：	e3
湿度敏感等级：	1	峰值回流温度（摄氏度）：	NOT SPECIFIED
端子面层：	Tin (Sn)	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

FDMF6820B 数据手册

Pin Configuration

Figure 3.

Bottom View

Figure 4.

Top View

Pin Definitions

Pin #

Name

Description

When SMOD#=HIGH, the low-side driver is the inverse of the PWM input. When

SMOD# SMOD#=LOW, the low-side driver is disabled. This pin has a 10 µA internal pull-up current

source. Do not add a noise filter capacitor.

VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND.

Power for the gate driver. Minimum 1 µF ceramic capacitor is recommended to be connected

VDRV

as close as possible from this pin to CGND.

Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a

bootstrap capacitor from this pin to PHASE.

BOOT

5, 37, 41 CGND IC ground. Ground return for driver IC.

For manufacturing test only. This pin must float; it must not be connected to any pin.

PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

No connect. The pin is not electrically connected internally, but can be connected to VIN for

convenience.

9 - 14, 42

VIN

Power input. Output stage supply voltage.

15, 29 -

35, 43

Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point

for the adaptive shoot-through protection.

VSWH

16 – 28

PGND Power ground. Output stage ground. Source pin of the low-side MOSFET.

For manufacturing test only. This pin must float; it must not be connected to any pin.

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the

output is pulled LOW. THWN# does not disable the module.

THWN#

Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are

DISB# held LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter

capacitor.

PWM PWM signal input. This pin accepts a three-state 3.3 V PWM signal from the controller.

FDMF6820B • Rev. 1.0.3

www.fairchildsemi.com

1 2 345 6 7...21

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