Adaptive Gate Drive Circuit
The driver IC design ensures minimum MOSFET dead
time while eliminating potential shoot-through (cross-
conduction) currents. It senses the state of the
MOSFETs and adjusts the gate drive adaptively to
prevent simultaneous conduction. Figure 25 provides
the relevant timing waveforms. To prevent overlap
during the LOW-to-HIGH switching transition (Q2 off to
Q1 on), the adaptive circuitry monitors the voltage at the
GL pin. When the PWM signal goes HIGH, Q2 begins to
turn off after a propagation delay (tPD_PHGLL). Once the
GL pin is discharged below ~1V, Q1 begins to turn on
To prevent overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the VSWH pin. When the PWM signal goes
LOW, Q1 begins to turn off after a propagation delay
(tPD_PLGHL). Once the VSWH pin falls below ~2.2V, Q2
begins to turn on after adaptive delay tD_DEADOFF
.
Additionally, VGS(Q1) is monitored. When VGS(Q1) is
discharged below ~1.2V, a secondary adaptive delay is
initiated that results in Q2 being driven on after
tD_TIMEOUT, regardless of VSWH state. This function is
implemented to ensure CBOOT is recharged each
switching cycle in the event that the VSWH voltage does
not fall below the 2.2V adaptive threshold. Secondary
after adaptive delay tD_DEADON
.
delay tD_TIMEOUT is longer than tD_DEADOFF
.
VIH_PWM
VIH_PWM
VIH_PWM
VIH
VTRI_HI
PWM
VTRI_HI
VTRI_LO
VIL_PWM
IL_PWM
V
tR_GH
tF_GH
PWM
less than
tD_HOLD
90%
10%
tD_HOLD ‐
OFF
OFF
‐
GH
to
VSWH
VIN
DCM
CCM
DCM
VOUT
2.2V
VSWH
GL
90%
90%
10%
1.0V
10%
tPD_PLGHL
tPD_PHGLL
tD_DEADON
less than
tF_GL
tR_GL
tPD_TSGHH
tD_HOLD
tPD_TSGHH tD_HOLD ‐OFF
‐OFF tPD_TSGLH
tD_HOLD
OFF
‐
tD_DEADOFF
Exit
3 State
Enter
3‐State
Enter
Enter
3 ‐State
Exit
3‐State
Exit
3‐State
3 ‐State
Notes:
PD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.
tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)
t
Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW)
PWM
Exiting 3‐state
tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS
tPD_TSGHH = PWM 3‐state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS
tPD_TSGLH = PWM 3‐state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS
t
PD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS
tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW)
SMOD#
Dead Times
t
PD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS
tD_DEADON = LS VGS fall to HS VGS rise, LS‐comp trip value (~1.0V GL) to 10% HS VGS
tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS
tD_DEADOFF = VSWH fall to LS VGS rise, SW‐comp trip value (~2.2V VSWH) to 10% LS VGS
Figure 25. PWM and 3-StateTiming Diagram
© 2011 Fairchild Semiconductor Corporation
FDMF6707V • Rev. 1.0.3
www.fairchildsemi.com
12