Marking Information
F- Fairchild Logo
Z: Assembly Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: Package Type (MP=MLP)
M: Manufacture Flow Code
ZXYTT
FAN501A
TM
Figure 4.
Top Mark
Pin Configuration
HV
8
SD
7
6
5
FB
CS
9
SGND
COMP
FAN501A
PGND 10
4
1
2
3
GATE VDD
Figure 5.
VS
Pin Assignments
Pin Definitions
Pin #
Name
Description
PWM Signal Output. This pin has an internal totem-pole output driver to drive the power
MOSFET. The gate driving voltage is internally clamped at 7.5 V.
1
GATE
Power Supply. IC operating current and MOSFET driving current are supplied through this pin.
This pin is typically connected to an external capacitor.
2
3
VDD
VS
Voltage Sense. This pin detects the output voltage information and diode current discharge time
based on the voltage of the auxiliary winding. It also senses sink current through the auxiliary
winding to detect input voltage information.
CC Control Correction. This pin connects to external resistor to program the CC control
correction weighting.
4
5
COMP
SGND
Signal Ground
Feedback. An opto-coupler is typically connected to this pin to provide feedback information to
the internal PWM comparator. This feedback is used to control the duty cycle in Constant-
Voltage (CV) regulation.
6
FB
Shut Down. This pin is implemented for external over-temperature protection by connecting to
an NTC thermistor.
7
8
SD
HV
High Voltage. This pin connects to a DC bus for high-voltage startup.
Current Sense. This pin connects to a current-sense resistor to detect the MOSFET current for
Peak-Current-Mode control for output regulation. The current-sense information is also used to
estimate the output current for CC regulation.
9
CS
10
PGND
Power Ground
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
3