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FAN3121C

更新时间： 2024-01-26 08:57:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器栅极栅极驱动
页数 文件大小 规格书
12页 459K
描述
Application Review and Comparative Evaluation of Low-Side Gate Drivers

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FAN3121C 技术参数

是否无铅：不含铅生命周期：Active
包装说明：SOP, SOP8,.25Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
Factory Lead Time：1 week风险等级：1.39
Is Samacsys：N内置保护：UNDER VOLTAGE
高边驱动器：NO接口集成电路类型：BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码：R-PDSO-G8JESD-609代码：e4
长度：5 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
输出电流流向：SOURCE AND SINK封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：12 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：MOSFET Drivers最大压摆率：0.9 mA
最大供电电压：18 V最小供电电压：4.5 V
标称供电电压：12 V表面贴装：YES
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
断开时间：0.035 µs接通时间：0.035 µs
宽度：4 mmBase Number Matches：1

FAN3121C 数据手册

 浏览型号FAN3121C的Datasheet PDF文件第6页浏览型号FAN3121C的Datasheet PDF文件第7页浏览型号FAN3121C的Datasheet PDF文件第8页浏览型号FAN3121C的Datasheet PDF文件第10页浏览型号FAN3121C的Datasheet PDF文件第11页浏览型号FAN3121C的Datasheet PDF文件第12页 
AN-6069  
APPLICATION NOTE  
In both these circuits, there is a voltage transient that may  
last for 50-100ns as the current increases to the limits of the  
driver. A compact layout using surface mount components  
keeps the loop area small to minimize parasitic inductance.  
The two previous circuits require a unique surface mount  
layout. It is possible to evaluate driver current capability by  
connecting a relatively large capacitive load on the output of  
a driver with the simple circuit shown in Figure 21.  
Figure 22. Compound Driver Current Source  
Waveforms  
Figure 22 shows the leading spike across the inductance  
introduced by the wire loop inserted in the circuit to enable  
use of a current probe. If the wire loop is removed and the  
0.1µF surface mount capacitor is installed in a layout with  
minimal parasitic inductance, the waveforms shown in  
Figure 23 are obtained. In short intervals where the voltage  
waveform is approximately linear, the basic relation is:  
Figure 21. "Large" Load Test Circuit  
dV  
⎛
⎜
⎞
⎟
For a starting point, CLOAD is chosen to be 100 times larger  
than the load used for rise and fall time measurements and  
the input is driven with a 1kHz square wave. On typical  
datasheets, 2A drivers are specified with 1nF load for the  
rise and fall time specifications, so CLOAD would be selected  
to be 0.1µF. This relatively large load prevents the output  
from changing rapidly, allowing the driver output current to  
reach its internal limiting value. A current probe, IPRB, can  
be used to monitor the output current along with the output  
voltage VOUT on an oscilloscope. This enables plotting the  
output current available at the corresponding output voltage.  
Bench comparisons have shown that the current  
OUT  
I = CLOAD  
⋅
(16)  
dT  
⎝
⎠
can be applied to provide an estimate of the current.  
measurement obtained using this method agrees closely with  
that obtained using the clamp circuits in Figure 19 and  
Figure 20. In addition, the slower current rise and fall times  
allow the current measurements to be made comfortably  
within the bandwidth limits of a current probe.  
Figure 23. Compound Driver Current Estimation  
Figure 22 shows the waveforms obtained using the test  
circuit shown in Figure 21 to evaluate a 2A sink / 1.5A  
source driver (FAN3227C) with a compound output stage.  
When the driver input, VIN, goes high, there is a transient  
glitch on the VOUT trace as the output current quickly  
increases to 3A through the inductance of the current probe  
loop. After approximately 70ns, the current has reached its  
peak value and the voltage spike across the parasitic  
inductances vanishes. With VOUT = 6V, the output current is  
measured as 1.5A (source current).  
The oscillogram in Figure 23 allows calculation of current  
during the cursor interval as:  
1.131V  
40.6ns  
⎛
⎜
⎞
⎟
I = 0.1µF⋅  
= 2.8A  
(17)  
⎝
⎠
providing close agreement with the peak value seen in the  
OUT trace in Figure 22. A similar calculation around VOUT  
I
=
6V provides a current estimation of 1.5A, nearly identical to  
the result obtained with direct current measurement using a  
current probe. The close agreement between the current  
measurement techniques using the large load helps develop  
confidence in the results obtained.  
© 2007 Fairchild Semiconductor Corporation  
Rev. 1.0.3 • 1/6/10  
www.fairchildsemi.com  
9
1...6789101112

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