Datasheet > F528L-80.000MHZ

F528L-80.000MHZ

更新时间： 2023-08-15 00:00:00

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FOX		/
页数	文件大小	规格书
2页	167K
描述
HCMOS Output Clock Oscillator, 80MHz Nom, ROHS COMPLIANT, SMD, 4 PIN

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F528L-80.000MHZ 数据手册

HcMOS 5x3.2mm 2.85V SMD Osꢀiꢁꢁator

Rev. 5/7/2009

RoHS compꢁiant / Pꢂ Free

Modeꢁ: F520l Series

http://www.foxonline.com/need_a_sample.htm

Page 1 of 2

FEATURES

• 2.85V Operation

OPTIONS

• 5.0V (F550L) Version Available

• HCMOS Output

• Standby Function

• Tape and Reel (1,000 pcs. STD)

• PART NUMbER SElEcTION^{Learn More - Internet Required}

5.0 ± 0.2

Model

Frequency

Operating

Frequency

# 4

# 3

Part Number

Stability¹Temperature (ºC) Range (MHz)

Number

661-Frequency-xxxxx F520L

662-Frequency-xxxxx F520LR ±100PPM

±100PPM

-10 ~ +70

-40 ~ +85

-10 ~ +70

-40 ~ +85

-10 ~ +70

-40 ~ +85

-10 ~ +70

1.544 ~ 80.000

Top

3.2 ± 0.2

View

663-Frequency-xxxxx F525L

664-Frequency-xxxxx F525LR

499-Frequency-xxxxx F526L

659-Frequency-xxxxx F526LR ±25PPM*

520-Frequency-xxxxx F528L

±20PPM*

±50PPM

±25PPM

Dot denotes

pin 1

# 2

# 1

1.3 Max

• ElEcTRIcAl cHARAcTERISTIcS

MAX (unless otherwise noted)

PARAMETERS

Frequency Range (FO)

Storage Temperature Range (TSTG)

1.544 ~ 80.000 MHz

-55ºC ~ +125ºC

2.85V ± 5%

2.54±0

Supply Voltage

Input Current

(VDD)

(IDD)

# 2

# 1

Bottom

View

1.544 ~ 32.000 MHz

32.000+ ~ 50.000 MHz

50.000+ ~ 80.000 MHz

Output Symmetry (50% VDD)

Rise Time (10% ~ 90% VDD) (TR)

Fall Time (90% ~ 10% VDD) (TF)

12mA

20mA

40mA

45% ~ 55%

5nS

# 3

# 4

1.2

1.0

5nS

Recommended

Output Voltage

(VOL)

10% VDD

90% VDD Min

4mA Min

-4mA Min

15pF

Solder Pad Layout

(VOH)

2.54

Output Current

(IOL)

(IOH)

1.29

Output Load

(HCMOS)

Standby Current

Start-up Time

10µA

10mS

150nS

10mS

2.25

(TS)

Output Disable Time ²

Output Enable Time ²

1.24

¹Inclusive of 25ºC tolerance, operating temperature range, input voltage change, load change, aging,

shock, and vibration. *Excludes Shock/Vibration

²An internal pullup resistor from pin 1 to pin 4 allows active output if pin 1 is left open.

Note: A 0.01µF bypass capacitor should be placed between VDD (Pin 4) and GND (Pin 2) to

minimize power supply line noise.

Drawing is for reference to critical speciﬁcations deﬁned by size measurements.

Certain non-critical visual attributes, such as side castellations, reference pin shape, etc. may vary.

All speciﬁcations subject to change without notice.

Pin Connections

#1 E/D

#3 Output

#4 V DD

#2 GND

• ENAblE / DISAblE FUNcTION

INH (Pin 1)

OPEN ²

OUTPUT (Pin 3)

ACTIVE

'1' Level VIH ≥ 70% VDD

'0' Level VIL ≤ 30% VDD

ACTIVE

High Z

FOXElectronics 5570 Enterprise Parkway Fort Myers, Florida 33905 USA +1.239.693.0099 FAX +1.239.693.1554 http://www.foxonline.com

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