TMS320F280025, TMS320F280025-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
TMS320F28002x Real-Time Microcontrollers
•
Analog system
– Two 3.45-MSPS, 12-bit Analog-to-Digital
Converters (ADCs)
1 Features
•
TMS320C28x 32-bit DSP core at 100 MHz
– IEEE 754 Floating-Point Unit (FPU)
Support for Fast Integer Division (FINTDIV)
– Trigonometric Math Unit (TMU)
•
•
Up to 16 external channels
Four integrated Post-Processing Blocks
(PPB) per ADC
•
•
Support for Nonlinear Proportional Integral
Derivative (NLPID) control
– Four windowed comparators (CMPSS) with
12-bit reference Digital-to-Analog Converters
(DACs)
– CRC Engine and Instructions (VCRC)
– Ten hardware breakpoints (with ERAD)
On-chip memory
– 128KB (64KW) of flash (ECC-protected)
– 24KB (12KW) of RAM (ECC or parity-protected)
– Dual-zone security
•
Digital glitch filters
•
•
•
Enhanced control peripherals
– 14 ePWM channels with eight channels that
have high-resolution capability (150-ps
resolution)
•
•
Integrated dead-band support
Integrated hardware trip zones (TZs)
Clock and system control
– Two internal zero-pin 10-MHz oscillators
– On-chip crystal oscillator or external clock input
– Windowed watchdog timer module
– Missing clock detection circuitry
– Dual-clock Comparator (DCC)
Single 3.3-V supply
– Internal VREG generation
– Brownout reset (BOR) circuit
System peripherals
– Three Enhanced Capture (eCAP) modules
•
High-resolution Capture (HRCAP) available
on one of the three eCAP modules
– Two Enhanced Quadrature Encoder Pulse
(eQEP) modules with support for CW/CCW
operation modes
Configurable Logic Block (CLB)
– Augments existing peripheral capability
– Supports position manager solutions
Host Interface Controller (HIC)
– Access to internal memory from an external
host
Background CRC (BGCRC)
– One cycle CRC computation on 32 bits of data
Diagnostic features
– Memory Power On Self Test (MPOST)
– Hardware Built-in Self Test (HWBIST)
Package options:
– 80-pin Low-profile Quad Flatpack (LQFP)
[PN suffix]
– 64-pin LQFP [PM suffix]
– 48-pin LQFP [PT suffix]
Temperature options:
– S: –40°C to 125°C junction
– Q: –40°C to 125°C free-air
(AEC Q100 qualification for automotive
applications)
•
•
•
•
– 6-channel Direct Memory Access (DMA)
controller
– 39 individually programmable multiplexed
General-Purpose Input/Output (GPIO) pins
– 16 digital inputs on analog pins
– Enhanced Peripheral Interrupt Expansion
(ePIE)
– Multiple low-power mode (LPM) support
– Embedded Real-time Analysis and Diagnostic
(ERAD)
– Unique Identification (UID) number
Communications peripherals
– One Power-Management Bus (PMBus)
interface
– Two Inter-integrated Circuit (I2C) interfaces
– One Controller Area Network (CAN) bus port
– Two Serial Peripheral Interface (SPI) ports
– One UART-compatible Serial Communication
Interface (SCI)
•
•
•
•
•
– Two UART-compatible Local Interconnect
Network (LIN) interfaces
– Fast Serial Interface (FSI) with one transmitter
and one receiver (up to 200Mbps)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
Copyright © 2020 Texas Instruments Incorporated
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1
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