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EVAL-ADF7020DBZ3 PDF预览

EVAL-ADF7020DBZ3

更新时间: 2022-04-14 19:30:13
品牌 Logo 应用领域
亚德诺 - ADI ISM频段
页数 文件大小 规格书
48页 719K
描述
High Performance, ISM Band, FSK/ASK Transceiver IC

EVAL-ADF7020DBZ3 数据手册

 浏览型号EVAL-ADF7020DBZ3的Datasheet PDF文件第39页浏览型号EVAL-ADF7020DBZ3的Datasheet PDF文件第40页浏览型号EVAL-ADF7020DBZ3的Datasheet PDF文件第41页浏览型号EVAL-ADF7020DBZ3的Datasheet PDF文件第43页浏览型号EVAL-ADF7020DBZ3的Datasheet PDF文件第44页浏览型号EVAL-ADF7020DBZ3的Datasheet PDF文件第45页 
ADF7020  
Data Sheet  
REGISTER 8—POWER-DOWN TEST REGISTER  
LOG AMP/  
RSSI  
CONTROL  
BITS  
DB10 DB9  
DB1  
DB2  
DB0  
DB7  
PD4  
DB13 DB12 DB11  
DB8  
PD5  
DB6  
PD3  
DB5  
PD2  
DB4  
PD1  
DB3  
SW1  
LR2  
LR1  
PD6  
C4(1) C3(0) C2(0) C1(0)  
PD7  
PD7 PA (Rx MODE)  
PLE1  
LOOP  
PD2 PD1  
(FROM REG 0)  
CONDITION  
0
1
PA OFF  
PA ON  
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
VCO/PLL OFF  
PLL ON  
VCO ON  
PLL/VCO ON  
PLL/VCO ON  
SW1 Tx/Rx SWITCH  
0
1
DEFAULT (ON)  
OFF  
PD3 LNA/MIXER ENABLE  
LR2 LR1 RSSI MODE  
0
1
LNA/MIXER OFF  
LNA/MIXER ON  
X
X
0
1
RSSI OFF  
RSSI ON  
PD6 DEMOD ENABLE  
PD4 FILTER ENABLE  
0
1
DEMOD OFF  
DEMOD ON  
0
1
FILTER OFF  
FILTER ON  
PD5 ADC ENABLE  
0
1
ADC OFF  
ADC ON  
Figure 53. Register 8—Power-Down Test Register  
Register 8—Power-Down Test Register Comments  
For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.  
It is not necessary to write to this register under normal operating conditions.  
Rev. D | Page 42 of 48  
 

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