5秒后页面跳转
捷配首页

Datasheet > 电信电路 > 编解码器> ETC5054D
ETC5054D PDF预览

ETC5054D

更新时间： 2024-01-26 18:09:10
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器过滤器编解码器电信集成电路电信电路光电二极管LTEPC
页数 文件大小 规格书
18页 155K
描述
SERIAL INTERFACE CODEC/FILTER

阅读下载

获取价格

ETC5054D 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.91
压伸定律：MU-LAW滤波器：YES
最大增益公差：0.15 dBJESD-30 代码：R-PDIP-T16
JESD-609代码：e0线性编码：NOT AVAILABLE
负电源额定电压：-5 V功能数量：1
端子数量：16工作模式：SYNCHRONOUS/ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：+-5 V认证状态：Not Qualified
座面最大高度：5.1 mm子类别：Codecs
最大压摆率：11 mA标称供电电压：5 V
表面贴装：NO技术：CMOS
电信集成电路类型：PCM CODEC温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

ETC5054D 数据手册

 浏览型号ETC5054D的Datasheet PDF文件第2页浏览型号ETC5054D的Datasheet PDF文件第3页浏览型号ETC5054D的Datasheet PDF文件第4页浏览型号ETC5054D的Datasheet PDF文件第6页浏览型号ETC5054D的Datasheet PDF文件第7页浏览型号ETC5054D的Datasheet PDF文件第8页 
ETC5054 - ETC5057  
edges clock out the remaining seven bits. The DX  
output is disabled by the falling BCLKX edge fol-  
lowing the eighth rising edge, or by FSX going  
low, which-ever comes later. A rising edge on the  
receive frame sync pulse, FSR, will cause the  
PCM data at DR to be latched in on the next eight  
falling edges of BCLKR (BCLKX in synchronous  
mode). Both devices may utilize the long frame  
sync pulse in synchronous or asynchronous  
mode.  
proximation encoding cycle begins. The 8-bit  
code is then loaded into a buffer and shifted out  
through DX at the next FSX pulse. The total en-  
coding delay will be approximately 165 µs (due to  
µ
the transmit filter) plus 125 s (due to encoding  
delay), which totals 290µs. Any offset vol-tage  
due to the filters or comparator is cancelled by  
sign bit integration.  
RECEIVE SECTION  
The receive section consists of an expanding  
DAC which drives a fifth order switched-capacitor  
low pass filter clocked at 256 kHz. The decoder is  
A-law (ETC5057) or µ–law (ETC5054) and the  
5th order low pass filter corrects for the sin x/x at-  
tenuation due to the 8 kHz sample and hold.  
The filter is then followed by a 2nd order RC ac-  
tive post-filter and power amplifier capable of driv-  
ing a 600Ω load to a level of 7.2 dBm. The re-  
ceive section is unity-gain. Upon the occurence of  
FSR, the data at the DR input is clocked in on the  
falling edge of the next eight BCLKR (BCLKX) pe-  
riods. At the end of the decoder time slot, the de-  
coding cycle begins, and 10µs later the decoder  
DAC output is updated. The total decoder delay  
TRANSMIT SECTION  
The transmit section input is an operational ampli-  
fier with provision for gain adjustment using two  
external resistors, see figure 6. The low noise and  
wide bandwidth allow gains in excess of 20 dB  
across the audio passband to be realized. The op  
amp drives a unitygain filter consisting of RD ac-  
tive pre-filter, followed by an eighth order  
switched-capacitor bandpass filter clocked at 256  
kHz. The output of this filter directly drives the en-  
coder sample-and-holdcircuit. The A/D is of com-  
panding type according to A-law (ETC5057) or µ–  
law (ETC5054) coding conventions. A precision  
voltage reference is trimmed in manufacturing to  
provide an input overload (tMAX) of nominally2.5V  
peak (see table of transmission characteristics).  
The FSX frame sync pulse controls the sampling  
of the filter output, and then the successive-ap-  
µ µ  
10 s (decoder update) plus 110 s (filter  
is  
delay) plus 62.5µs (1/2 frame), which gives ap-  
proximately 180µs. A mute circuitry is a active  
during 10ms when power up.  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
VCC  
Parameter  
Value  
Unit  
V
VCC to GNDA  
VBB to GNDA  
7
– 7  
VBB  
V
VIN, VOUT  
Voltage at any Analog Input or Output  
Voltage at Any Digital Input or Output  
Operating Temperature Range  
VCC + 0.3 to VBB – 0.3  
VCC + 0.3 to GNDA – 0.3  
– 25 to + 125  
– 65 to + 150  
300  
V
V
Toper  
Tstg  
C
C
C
°
°
°
Storage Temperature Range  
Lead Temperature (soldering, 10 seconds)  
ELECTRICAL OPERATING CHARACTERISTICS VCC = 5.0 V ± 5 %, VBB = – 5.0 V ± 5%GNDA = 0 V,  
TA = 0 °C to 70 °C; Typical Characteristics Specified at VCC = 5.0 V, VBB = – 5.0 V, TA = 25 °C ; all signals  
are referenced to GNDA.  
Symbol  
VIL  
VIH  
Parameter  
Min.  
Typ.  
Max.  
0.6  
Unit  
V
V
Input Low Voltage  
Input High Voltage  
2.2  
VOL  
Output Low Voltage  
IL = 3.2mA  
D X  
TSX  
0.4  
0.4  
V
V
IL = 3.2mA, Open Drain  
VOH  
Output High Voltage  
IH = 3.2mA  
D X  
2.4  
–10  
–10  
V
IIL  
IIH  
IOZ  
Input Low Current (GNDA ≤ VIN ≤ VIL, all digital inputs)  
Input High Current (VIH ≤ VIN ≤ VCC) except BCLKR/BCLKSEL  
Output Current in HIGH Impedance State (TRI-STATE)  
10  
10  
µA  
µA  
(GNDA ≤ VO ≤ VCC  
)
DX  
–10  
10  
µA  
5/18  
12345678...18

下载PDF

与ETC5054D相关器件

型号 品牌 描述 获取价格 数据表
ETC5054D-X ETC u-Law CODEC

获取价格
ETC5054D-X/HTR STMICROELECTRONICS MU-LAW, PCM CODEC, PDSO16, SOP-16

获取价格
ETC5054FN ETC u-Law CODEC

获取价格
ETC5054FN-X ETC u-Law CODEC

获取价格
ETC5054J ETC u-Law CODEC

获取价格
ETC5054J/G STMICROELECTRONICS IC,PCM CODEC,SINGLE,CMOS,DIP,16PIN,CERAMIC

获取价格

与ETC5054D相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证