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ES51969 PDF预览

ES51969

更新时间: 2022-12-28 03:36:49
品牌 Logo 应用领域
承永 - CYRUSTEK /
页数 文件大小 规格书
32页 560K
描述
6,600 Counts Auto DMM

ES51969 数据手册

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ES51969  
6,600 Counts Auto DMM  
Pin Description  
Pin No  
Symbol  
V+  
Type  
Description  
1
2
3
4
5
6
7
O
Output of on-chip DC-DC converter.  
CREF+  
CREF-  
CINT  
CAZ  
I/O Positive connection for reference capacitor.  
I/O Negative connection for reference capacitor.  
O
I
O
O
Integrator output. Connect to integral capacitor  
Auto-zero capacitor connection.  
Buffer output pin. Connect to integral resistor  
Buffer output pin in high-speed mode. Connect to high-speed integral  
resistor.  
BUFF  
RAZ  
8
9
IVSH  
IVSL  
OVX  
OHMC  
OVH  
OVSG  
OR1  
VR5  
VR4  
VR3  
VR2  
I
I
I
O
I
I
O
O
O
O
O
High current measurement input.  
Low current measurement input  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Input high voltage for resistance measurement  
Filter capacitor connection for resistance mode below 6.600Mrange.  
Output connection for resistance measurement  
Sense low voltage for resistance measurement  
Reference resistor connection for 660.0range  
Voltage measurement ÷10000 attenuator(1000V)  
Voltage measurement ÷1000 attenuator(660.0V)  
Voltage measurement ÷100 attenuator(66.00V)  
Voltage measurement ÷10 attenuator(6.600V)  
TEST5  
ACVL  
I/O Test pin  
O
DC signal low input in ACV/ACA mode. Connect to negative output of  
external AC to DC converter.  
21  
ACVH  
O
DC signal high input in ACV/ACA mode. Connect to positive output of  
external AC to DC converter.  
22  
23  
24  
25  
26  
27  
ADI  
ADO  
ADOHZ  
VRH  
VR  
I
O
I
O
I
Negative input of internal AC to DC OP Amp.  
Output of internal AC to DC OP Amp.  
Frequency input under voltage/current mode, offset to AGND.  
Output of band-gap voltage reference. Typically –1.2V  
Reference input voltage connection. Typically –400mV  
For ADP mode. De-integrating voltage positive input. The input should  
be higher than VA-.  
VA+  
I
28  
VA-  
I
For ADP mode. De-integrating voltage negative input. The input should  
be lower than VA+.  
29  
30  
31  
32  
33  
ADP  
SGND  
OHMC1  
VR1  
I
G
O
I
Measurement input in ADP mode.  
Signal Ground.  
Filter capacitor connection for resistance mode under 660.0Krange.  
Measurement input.  
In capacitance mode, a compensation capacitor is connected.  
In temperature mode, it is used to control decimal point.  
In µA or mA modes, pull to V- to disable the ‘µ2’ or ‘m2’ sign on LCD.  
Connect to a precise 9Kresister.  
VBAR  
I
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
R9K  
R1K  
CA-  
CA+  
CSH+  
CSH-  
OHMC2  
SLEEP  
FREQ  
RS232  
DSHIFT  
O
O
Connect to a precise 1Kresister.  
I/O Negative auto-zero capacitor connection for capacitor measurement  
I/O Positive auto-zero capacitor connection for capacitor measurement  
O
O
O
O
I
Positive connection to external capacitor.  
Negative connection to external capacitor.  
Filter capacitor connection for 6.600Mrange in resistance mode.  
Sleep mode indicator, asserts low in SLEEP mode.  
Frequency counter input, offset V-/2 internally by the chip.  
Assert low to enable serial data output.  
Pull to V- to have 0.01Mresolution in 66.00M.  
Pull to DGND or keep it float will change the resolution to 0.1M.  
Back light function. Pulse low to set BKOUT pin output.  
I
I
45  
BKLIT  
I
v2.6  
3
08/10/06  

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