Datasheet > ES1020QIT

ES1020QIT

更新时间： 2024-01-28 07:01:33

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
12页	800K
描述
Power Supply Support Circuit

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ES1020QIT 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.7
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT	Base Number Matches：	1

ES1020QIT 数据手册

Enpirion^®Power Datasheet

ES1020QI Power Sequencing Controller

ES1020QI

Datasheet

The Altera Enpirion ES1020QI is an integrated 4-channel

controlled-on/controlled-off power-supply sequencer

with supply monitoring, fault protection and a “sequence

completed” signal (RESET). For larger systems, more than

four supplies can be sequenced by simply connecting a

wire between the SYSRESET pins of cascaded ICs. The

ES1020QI uses a patented, micropower 7x charge pump to

drive four external low-cost NFET switch gates above the

supply rail by 5.3V. These ICs can be biased from 5V

down to 1.5V by any supply.

Features

• Enables Arbitrary Turn-on and Turn-off Sequencing of

Up to Four Power Supplies (0.7V to 5V)

• Operates From 1.5V to 5V Supply Voltage

• Supplies V_DD+5.3V of Charge Pumped Gate Drive

• Adjustable Voltage Slew Rate for Each Rail

• Multiple Sequencers Can be Daisy-Chained to Sequence

an Infinite Number of Independent Supplies

• Glitch Immunity

External resistors provide flexible voltage threshold

programming of monitored rail voltages. Delay and

sequencing are provided by external capacitors for

ramp-up and ramp-down.

• Undervoltage Lockout for Each Supply

• Low ENABLE Input

• QFN Package

Additional I/O is provided for indicating and driving

the RESET state in various configurations.

• Pb-free (RoHS-compliant)

Applications

• Graphics Cards

For volume applications, other programmable options

and features are available.

• FPGA/ASIC/Microprocessor/PowerPC Supply

Sequencing

• Network Routers

• Telecommunications Systems

VDD+5V

Q-PUMP

BIAS

VDD

LOCK OUT

1µA

DLY_ONX

1.26V

-1µA

1µA

DLY_OFFX

10ms

RISING DELAY

1.26V

GATEX

30µs

FILTER

UVLOX

FIGURE 1. TYPICAL ES1020QI APPLICATION

RESET

LOGIC

0.633V

150ms

RISING DELAY

SYSRST

FIGURE 2. ES1020QI Block Diagram

NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and

Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of

their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor

products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use

of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are

advised to obtain the latest version of device specifications before relying on any published information and before placing orders

for products or services.

ISO

9001:2008

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Registered

May 2014 Altera Corporation

10041

May 28, 2014

Rev A

12 3 4 5 6 7...12

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