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EPM7256BQC208-10 PDF预览

EPM7256BQC208-10

更新时间: 2024-01-28 19:54:29
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟LTE输入元件可编程逻辑
页数 文件大小 规格书
66页 436K
描述
EE PLD, 10ns, 256-Cell, CMOS, PQFP208, PLASTIC, QFP-208

EPM7256BQC208-10 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:FQFP, QFP208,1.2SQ,20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.11
Is Samacsys:N其他特性:YES
最大时钟频率:94.3 MHz系统内可编程:YES
JESD-30 代码:S-PQFP-G208JESD-609代码:e3
JTAG BST:YES长度:28 mm
湿度敏感等级:3专用输入次数:
宏单元数:256端子数量:208
最高工作温度:70 °C最低工作温度:
组织:0 DEDICATED INPUTS输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):245
电源:1.8/3.3,2.5 V可编程逻辑类型:EE PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:4.1 mm子类别:Programmable Logic Devices
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:28 mm
Base Number Matches:1

EPM7256BQC208-10 数据手册

 浏览型号EPM7256BQC208-10的Datasheet PDF文件第2页浏览型号EPM7256BQC208-10的Datasheet PDF文件第3页浏览型号EPM7256BQC208-10的Datasheet PDF文件第4页浏览型号EPM7256BQC208-10的Datasheet PDF文件第5页浏览型号EPM7256BQC208-10的Datasheet PDF文件第6页浏览型号EPM7256BQC208-10的Datasheet PDF文件第7页 
MAX 7000B  
Programmable Logic  
Device  
®
September 2005, ver. 3.5  
Data Sheet  
High-performance 2.5-V CMOS EEPROM-based programmable logic  
devices (PLDs) built on second-generation Multiple Array MatriX  
(MAX®) architecture (see Table 1)  
Features...  
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V  
MAX 7000A device families  
High-density PLDs ranging from 600 to 10,000 usable gates  
3.5-ns pin-to-pin logic delays with counter frequencies in excess  
of 303.0 MHz  
Advanced 2.5-V in-system programmability (ISP)  
Programs through the built-in IEEE Std. 1149.1 Joint Test Action  
Group (JTAG) interface with advanced pin-locking capability  
Enhanced ISP algorithm for faster programming  
ISP_Done bit to ensure complete programming  
Pull-up resistor on I/O pins during in-system programming  
ISP circuitry compliant with IEEE Std. 1532  
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V  
MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet.  
f
Table 1. MAX 7000B Device Features  
Feature  
EPM7032B  
EPM7064B  
EPM7128B  
EPM7256B  
EPM7512B  
Usable gates  
Macrocells  
600  
32  
2
1,250  
64  
2,500  
128  
8
5,000  
256  
16  
10,000  
512  
Logic array blocks  
4
32  
Maximum user I/O  
pins  
36  
68  
100  
164  
212  
t
PD (ns)  
SU (ns)  
3.5  
2.1  
3.5  
2.1  
4.0  
2.5  
5.0  
3.3  
5.5  
3.6  
t
tFSU (ns)  
CO1 (ns)  
1.0  
1.0  
1.0  
1.0  
1.0  
t
2.4  
2.4  
2.8  
3.3  
3.7  
fCNT (MHz)  
303.0  
303.0  
243.9  
188.7  
163.9  
Altera Corporation  
1
DS-MAX7000B-3.5  
 

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