Datasheet > EPM2210GF100I4ES

EPM2210GF100I4ES

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
98页	1060K
描述
Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, FBGA-100

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DC & Switching Characteristics

Table 5–30. External Timing Output Delay & t_ODAdders for Slow Slew Rate

-3 Speed Grade -4 Speed Grade

-5 Speed Grade

Unit

Standard

Min

Max

Min

Max

Min

Max

3.3-V LVTTL

16 mA

8 mA

4 mA

14 mA

7 mA

6 mA

3 mA

4 mA

2 mA

20 mA

7,064

7,946

7,064

7,946

10,434

11,548

22,927

24,731

38,723

41,330

261

6,745

7,627

6,745

7,627

10,115

11,229

22,608

24,412

38,404

41,011

339

6,426

7,308

6,426

7,308

9,796

10,910

22,289

24,093

38,085

40,692

418

3.3-V LVCMOS

2.5-V LVTTL

1.8-V LVTTL /

LVCMOS

1.5-V LVCMOS

3.3-V PCI

Table 5–31. MAX II IOE Programmable Delays

-3 Speed Grade -4 Speed Grade -5 Speed Grade

Parameter

Unit

Min

Max

Min

Max

Min

Max

Increase_input_delay_to_internal_cells=ON

Increase_input_delay_to_internal_cells=OFF

1,225

1,592

115

1,960

142

Maximum Input & Output Clock Rates

Tables 5–32 and 5–33 show the maximum input and output clock rates for

standard I/O pins in MAX II devices.

Table 5–32. MAX II Maximum Input Clock Rate for I/O (Part 1 of 2)

Standard -3 Speed Grade -4 Speed Grade -5 Speed Grade Unit

3.3-V LVTTL

Without Schmitt

304

MHz

Trigger

With Schmitt Trigger

250

304

250

304

250

304

MHz

3.3-V LVCMOS

Without Schmitt

Trigger

With Schmitt Trigger

250

MHz

Altera Corporation

July 2006

Core Version a.b.c variable

5–27

MAX II Device Handbook, Volume 1

1...90 91 929394 95 96...98

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STM32F103C8T6 替代型号

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