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EPM1270GM100I3N PDF预览

EPM1270GM100I3N

更新时间: 2022-12-01 20:54:51
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
98页 1060K
描述
Flash PLD, PBGA100, 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, MICRO, FBGA-100

EPM1270GM100I3N 数据手册

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Section I. MAX II Device  
Family Data Sheet  
This section provides designers with the data sheet specifications for  
MAX® II devices. The chapters contain feature definitions of the internal  
architecture, Joint Test Action Group (JTAG) and in-system  
programmability (ISP) information, DC operating conditions, AC timing  
parameters, and ordering information for MAX II devices.  
This section includes the following chapters:  
Chapter 1. Introduction  
Chapter 2. MAX II Architecture  
Chapter 3. JTAG & In-System Programmability  
Chapter 4. Hot Socketing & Power-On Reset in MAX II Devices  
Chapter 5. DC & Switching Characteristics  
Chapter 6. Reference & Ordering Information  
The table below shows the revision history for Chapters 1 through 6.  
Revision History  
Chapter(s)  
Date/Version  
August 2006, v1.5  
July 2006, v1.4  
June 2005, v1.3  
Changes Made  
Minor update to features list.  
Minor updates to tables.  
1
Updated timing numbers in Table 1-1.  
December 2004, v1.2 Updated timing numbers in Table 1-1.  
Updated timing numbers in Table 1-1.  
June 2004, v1.1  
2
Updated functional description and I/O  
August 2006, v1.6  
structure sections.  
Altera Corporation  
Section I–1  
Preliminary  

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