Datasheet > EPF8636A

EPF8636A

更新时间： 2022-11-26 09:14:01

品牌	Logo	应用领域
阿尔特拉 - ALTERA		可编程逻辑器件
页数	文件大小	规格书
61页	911K
描述
PROGRAMMABLE LOGIC DEVICES FAMILY

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EPF8636A 数据手册

FLEX 8000 Programmable Logic Device Family Data Sheet

Figure 1 shows a block diagram of the FLEX 8000 architecture. Each

group of eight LEs is combined into an LAB; LABs are arranged into rows

and columns. The I/O pins are supported by I/O elements (IOEs) located

at the ends of rows and columns. Each IOE contains a bidirectional I/O

buffer and a flipflop that can be used as either an input or output register.

Figure 1. FLEX 8000 Device Block Diagram

IOE

I/O Element

(IOE)

IOE

FastTrack

Interconnect

Logic Array

Block (LAB)

IOE

Logic

Element (LE)

IOE

Signal interconnections within FLEX 8000 devices and between device

pins are provided by the FastTrack Interconnect, a series of fast,

continuous channels that run the entire length and width of the device.

IOEs are located at the end of each row (horizontal) and column (vertical)

FastTrack Interconnect path.

Altera Corporation

1 2 3 456 7 8...61

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型号	品牌	描述	获取价格	数据表
EPF8636AGC192-2	ALTERA	Loadable PLD, CMOS, CPGA192, CERAMIC, PGA-192	获取价格
EPF8636AGC192-3	ETC	Field Programmable Gate Array (FPGA)	获取价格
EPF8636AGI192-3	ALTERA	Loadable PLD, CMOS, CPGA192, CERAMIC, PGA-192	获取价格
EPF8636AGI192-4	ALTERA	Loadable PLD, CMOS, CPGA192, CERAMIC, PGA-192	获取价格
EPF8636AGI192-A-4	ALTERA	Loadable PLD, 1.9ns, CMOS, CPGA192, PGA-192	获取价格
EPF8636AGM192-3	ALTERA	Loadable PLD, CMOS, CPGA192, PGA-192	获取价格