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EPF10K20RC208-4 PDF预览

EPF10K20RC208-4

更新时间: 2024-01-16 07:00:23
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件输入元件LTE时钟
页数 文件大小 规格书
128页 1707K
描述
Embedded Programmable Logic Device Family

EPF10K20RC208-4 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:HFQFP, HQFP208,1.2SQ,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.16Is Samacsys:N
其他特性:1152 LOGIC ELEMENTS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V最大时钟频率:67.11 MHz
JESD-30 代码:S-PQFP-G208JESD-609代码:e3
长度:28 mm湿度敏感等级:3
专用输入次数:4I/O 线路数量:147
输入次数:147逻辑单元数量:1152
输出次数:147端子数量:208
最高工作温度:70 °C最低工作温度:
组织:4 DEDICATED INPUTS, 147 I/O输出函数:REGISTERED
封装主体材料:PLASTIC/EPOXY封装代码:HFQFP
封装等效代码:HQFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, FINE PITCH峰值回流温度(摄氏度):245
电源:3.3/5 V可编程逻辑类型:LOADABLE PLD
传播延迟:0.6 ns认证状态:Not Qualified
座面最大高度:4.1 mm子类别:Field Programmable Gate Arrays
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:28 mm
Base Number Matches:1

EPF10K20RC208-4 数据手册

 浏览型号EPF10K20RC208-4的Datasheet PDF文件第1页浏览型号EPF10K20RC208-4的Datasheet PDF文件第3页浏览型号EPF10K20RC208-4的Datasheet PDF文件第4页浏览型号EPF10K20RC208-4的Datasheet PDF文件第5页浏览型号EPF10K20RC208-4的Datasheet PDF文件第6页浏览型号EPF10K20RC208-4的Datasheet PDF文件第7页 
FLEX 10K Embedded Programmable Logic Device Family Data Sheet  
Table 2. FLEX 10K Device Features  
Feature  
EPF10K70  
EPF10K100  
EPF10K100A  
EPF10K130V  
EPF10K250A  
Typical gates (logic and  
70,000  
100,000  
130,000  
250,000  
RAM) (1)  
Maximum system gates  
118,000  
3,744  
468  
158,000  
4,992  
624  
211,000  
6,656  
832  
310,000  
12,160  
1,520  
20  
LEs  
LABs  
EABs  
9
12  
16  
Total RAM bits  
Maximum user I/O pins  
18,432  
358  
24,576  
406  
32,768  
470  
40,960  
470  
Note to tables:  
(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum  
system gates.  
Devices are fabricated on advanced processes and operate with  
a 3.3-V or 5.0-V supply voltage (see Table 3  
In-circuit reconfigurability (ICR) via external configuration  
device, intelligent controller, or JTAG port  
...and More  
Features  
ClockLockTM and ClockBoostTM options for reduced clock  
delay/skew and clock multiplication  
Built-in low-skew clock distribution trees  
100% functional testing of all devices; test vectors or scan chains  
are not required  
Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices  
5.0-V Devices  
3.3-V Devices  
EPF10K10  
EPF10K20  
EPF10K30  
EPF10K40  
EPF10K50  
EPF10K70  
EPF10K100  
EPF10K10A  
EPF10K30A  
EPF10K50V  
EPF10K100A  
EPF10K130V  
EPF10K250A  
2
Altera Corporation  

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