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EP4CE55F23C7 PDF预览

EP4CE55F23C7

更新时间: 2024-02-13 13:18:44
品牌 Logo 应用领域
英特尔 - INTEL
页数 文件大小 规格书
44页 663K
描述
Field Programmable Gate Array, 3491 CLBs, 472.5MHz, 55856-Cell, PBGA484, 23 X 23 MM, 1 MM PITCH, FBGA-484

EP4CE55F23C7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-484针数:484
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.21最大时钟频率:472.5 MHz
JESD-30 代码:S-PBGA-B484JESD-609代码:e1
长度:23 mm湿度敏感等级:3
可配置逻辑块数量:3491输入次数:327
逻辑单元数量:55856输出次数:327
端子数量:484最高工作温度:85 °C
最低工作温度:组织:3491 CLBS
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA484,22X22,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
电源:1.2,1.2/3.3,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:2.4 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.25 V
最小供电电压:1.15 V标称供电电压:1.2 V
表面贴装:YES温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:23 mm
Base Number Matches:1

EP4CE55F23C7 数据手册

 浏览型号EP4CE55F23C7的Datasheet PDF文件第3页浏览型号EP4CE55F23C7的Datasheet PDF文件第4页浏览型号EP4CE55F23C7的Datasheet PDF文件第5页浏览型号EP4CE55F23C7的Datasheet PDF文件第7页浏览型号EP4CE55F23C7的Datasheet PDF文件第8页浏览型号EP4CE55F23C7的Datasheet PDF文件第9页 
1–6  
Chapter 1: Cyclone IV Device Datasheet  
Operating Conditions  
Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 2 of 2)  
Symbol  
VCCA_GXB  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Transceiver PMA and auxiliary power  
supply  
2.375  
2.5  
2.625  
V
Transceiver PMA and auxiliary power  
supply  
VCCL_GXB  
1.16  
1.2  
1.24  
V
VI  
DC input voltage  
DC output voltage  
–0.5  
0
3.6  
VCCIO  
85  
V
V
VO  
For commercial use  
For industrial use  
Standard power-on reset  
0
°C  
°C  
TJ  
Operating junction temperature  
–40  
100  
50 µs  
50 µs  
50 ms  
3 ms  
10  
(7)  
(POR)  
tRAMP  
Power supply ramp time  
(8)  
Fast POR  
Magnitude of DC current across  
PCI-clamp diode when enabled  
IDiode  
mA  
Notes to Table 1–4:  
(1) All VCCA pins must be powered to 2.5 V (even when PLLs are not used) and must be powered up and powered down at the same time.  
(2) You must connect VCCD_PLL to VCCINT through a decoupling capacitor and ferrite bead.  
(3) Power supplies must rise monotonically.  
(4) VCCIO for all I/O banks must be powered up during device operation. Configurations pins are powered up by VCCIO of I/O Banks 3, 8, and 9 where  
I/O Banks 3 and 9 only support VCCIO of 1.5, 1.8, 2.5, 3.0, and 3.3 V. For fast passive parallel (FPP) configuration mode, the VCCIO level of I/O  
Bank 8 must be powered up to 1.5, 1.8, 2.5, 3.0, and 3.3 V.  
(5) You must set VCC_CLKIN to 2.5 V if you use CLKIN as a high-speed serial interface (HSSI) refclk or as a DIFFCLK input.  
(6) The CLKIN pins in I/O Banks 3B and 8B can support single-ended I/O standard when the pins are used to clock left PLLs in non-transceiver  
applications.  
(7) The POR time for Standard POR ranges between 50 and 200 ms. VCCINT, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended  
operating range within 50 ms.  
(8) The POR time for Fast POR ranges between 3 and 9 ms. VCCINT, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended operating  
range within 3 ms.  
ESD Performance  
This section lists the electrostatic discharge (ESD) voltages using the human body  
model (HBM) and charged device model (CDM) for Cyclone IV devices general  
purpose I/Os (GPIOs) and high-speed serial interface (HSSI) I/Os. Table 1–5 lists the  
ESD for Cyclone IV devices GPIOs and HSSI I/Os.  
Table 1–5. ESD for Cyclone IV Devices GPIOs and HSSI I/Os  
Symbol  
VESDHBM  
Parameter  
ESD voltage using the HBM (GPIOs) (1)  
Passing Voltage  
Unit  
V
2000  
1000  
500  
(2)  
ESD using the HBM (HSSI I/Os)  
V
ESD using the CDM (GPIOs)  
V
VESDCDM  
(2)  
ESD using the CDM (HSSI I/Os)  
250  
V
Notes to Table 1–5:  
(1) The passing voltage for EP4CGX15 and EP4CGX30 row I/Os is 1000V.  
(2) This value is applicable only to Cyclone IV GX devices.  
Cyclone IV Device Handbook,  
Volume 3  
March 2016 Altera Corporation  

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