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EP3CLS200F780C8 PDF预览

EP3CLS200F780C8

更新时间: 2024-02-12 02:12:27
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟可编程逻辑
页数 文件大小 规格书
14页 306K
描述
Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780

EP3CLS200F780C8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:LEAD FREE, FBGA-780针数:780
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.39.00.01风险等级:5.27
最大时钟频率:450 MHzJESD-30 代码:S-PBGA-B780
JESD-609代码:e1长度:29 mm
湿度敏感等级:3可配置逻辑块数量:198464
输入次数:413逻辑单元数量:198464
输出次数:413端子数量:780
最高工作温度:85 °C最低工作温度:
组织:198464 CLBS封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA780,28X28,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):245电源:1.2,1.2/3.3,2.5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:2.4 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.25 V最小供电电压:1.15 V
标称供电电压:1.2 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:29 mm
Base Number Matches:1

EP3CLS200F780C8 数据手册

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1–4  
Chapter 1: Cyclone III Device Family Overview  
Cyclone III Device Family Features  
Table 1–2 lists Cyclone III device family package options, I/O pins, and differential  
channel counts.  
(1), (2), (3), (4), (5)  
Table 1–2. Cyclone III Device Family Package Options, I/O pin and Differential Channel Counts  
(7)  
Family  
Package E144  
M164  
P240  
F256  
U256  
F324  
F484  
U484  
F780  
EP3C5  
EP3C10  
94, 22 106, 28  
94, 22 106, 28  
182, 68 182, 68  
182, 68 182, 68  
EP3C16  
84, 19 92, 23 160, 47 168, 55 168, 55  
346, 140 346, 140  
EP3C25  
82, 18  
148, 43 156, 54 156, 54 215, 83  
Cyclone III  
(8)  
EP3C40  
128, 26  
195, 61 331, 127 331, 127 535, 227 (6)  
EP3C55  
327, 135 327, 135  
295, 113 295, 113  
377, 163  
429, 181  
531, 233  
429, 181  
429, 181  
429, 181  
429, 181  
EP3C80  
EP3C120  
EP3CLS70  
EP3CLS100  
EP3CLS150  
EP3CLS200  
283, 106  
294, 113 294, 113  
294, 113 294, 113  
Cyclone III  
LS  
226, 87  
226, 87  
Notes to Table 1–2:  
(1) For each device package, the first number indicates the number of the I/O pin; the second number indicates the differential channel count.  
(2) For more information about device packaging specifications, refer to the Cyclone III Package and Thermal Resistance webpage.  
(3) The I/O pin numbers are the maximum I/O counts (including clock input pins) supported by the device package combination and can be affected  
by the configuration scheme selected for the device.  
(4) All packages are available in lead-free and leaded options.  
(5) Vertical migration is not supported between Cyclone III and Cyclone III LS devices.  
(6) The EP3C40 device in the F780 package supports restricted vertical migration. Maximum user I/Os are restricted to 510 I/Os if you enable  
migration to the EP3C120 and are using voltage referenced I/O standards. If you are not using voltage referenced I/O standards, you can increase  
the maximum number of I/Os.  
(7) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground  
plane on your PCB. Use this exposed pad for electrical connectivity and not for thermal purposes.  
(8) All Cyclone III device UBGA packages are supported by the Quartus II software version 7.1 SP1 and later, with the exception of the UBGA  
packages of EP3C16, which are supported by the Quartus II software version 7.2.  
Cyclone III Device Handbook  
Volume 1  
July 2012 Altera Corporation  
 
 
 
 
 
 
 
 
 

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