Datasheet > EP3CLS200F780C8

EP3CLS200F780C8

更新时间： 2024-02-02 19:15:35

品牌	Logo	应用领域
阿尔特拉 - ALTERA		时钟栅可编程逻辑
页数	文件大小	规格书
14页	306K
描述
Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780

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EP3CLS200F780C8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	LEAD FREE, FBGA-780	针数：	780
Reach Compliance Code：	unknown	ECCN代码：	3A991
HTS代码：	8542.39.00.01	风险等级：	5.27
最大时钟频率：	450 MHz	JESD-30 代码：	S-PBGA-B780
JESD-609代码：	e1	长度：	29 mm
湿度敏感等级：	3	可配置逻辑块数量：	198464
输入次数：	413	逻辑单元数量：	198464
输出次数：	413	端子数量：	780
最高工作温度：	85 °C	最低工作温度：
组织：	198464 CLBS	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA780,28X28,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	245	电源：	1.2,1.2/3.3,2.5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	2.4 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	1.25 V	最小供电电压：	1.15 V
标称供电电压：	1.2 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	29 mm
Base Number Matches：	1

EP3CLS200F780C8 数据手册

1–2

Chapter 1: Cyclone III Device Family Overview

Cyclone III Device Family Features

Design Security Feature

Cyclone III LS devices offer the following design security features:

■

Configuration security using advanced encryption standard (AES) with 256-bit

volatile key

■

Routing architecture optimized for design separation flow with the Quartus^®II

software

■

Design separation flow achieves both physical and functional isolation

between design partitions

■

Ability to disable external JTAG port

Error Detection (ED) Cycle Indicator to core

■

Provides a pass or fail indicator at every ED cycle

■

Provides visibility over intentional or unintentional change of configuration

random access memory (CRAM) bits

■

Ability to perform zeroization to clear contents of the FPGA logic, CRAM,

embedded memory, and AES key

Internal oscillator enables system monitor and health check capabilities

Increased System Integration

■

High memory-to-logic and multiplier-to-logic ratio

■

High I/O count, low-and mid-range density devices for user I/O constrained

applications

■

Adjustable I/O slew rates to improve signal integrity

■

Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X,

LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS

■

Supports the multi-value on-chip termination (OCT) calibration feature to

eliminate variations over process, voltage, and temperature (PVT)

■

Four phase-locked loops (PLLs) per device provide robust clock management and

synthesis for device clock management, external system clock management, and

I/O interfaces

■

Five outputs per PLL

Cascadable to save I/Os, ease PCB routing, and reduce jitter

Dynamically reconfigurable to change phase shift, frequency multiplication or

division, or both, and input frequency in the system without reconfiguring the

device

■

Remote system upgrade without the aid of an external controller

Dedicated cyclical redundancy code checker circuitry to detect single-event upset

(SEU) issues

■

Nios^®II embedded processor for Cyclone III device family, offering low cost and

custom-fit embedded processing solutions

Cyclone III Device Handbook

Volume 1

July 2012 Altera Corporation

123 4 5 6 7...14

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与EP3CLS200F780C8相关器件

型号	品牌	描述	获取价格	数据表
EP3CLS200F780C8N	INTEL	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, LEAD FREE,	获取价格
EP3CLS200F780I7	ALTERA	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, 29 X 29 MM	获取价格
EP3CLS200F780I7	INTEL	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, 29 X 29 MM	获取价格
EP3CLS200F780I7N	INTEL	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, LEAD FREE,	获取价格
EP3CLS200F780I7N	ALTERA	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, LEAD FREE,	获取价格
EP3CLS70	ALTERA	Cyclone III Device Handbook	获取价格

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