5秒后页面跳转
EP2S90F1508C5ES PDF预览

EP2S90F1508C5ES

更新时间: 2024-02-10 10:14:30
品牌 Logo 应用领域
阿尔特拉 - ALTERA /
页数 文件大小 规格书
768页 5221K
描述
Stratix II Device Handbook, Volume 1

EP2S90F1508C5ES 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:BGA, BGA1508,39X39,40针数:1508
Reach Compliance Code:compliantECCN代码:3A001.A.7.A
HTS代码:8542.39.00.01风险等级:5.29
最大时钟频率:640 MHzCLB-Max的组合延迟:5.962 ns
JESD-30 代码:S-PBGA-B1508JESD-609代码:e1
长度:40 mm湿度敏感等级:3
可配置逻辑块数量:36384输入次数:902
逻辑单元数量:90960输出次数:894
端子数量:1508最高工作温度:85 °C
最低工作温度:组织:36384 CLBS
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA1508,39X39,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):245
电源:1.2,1.5/3.3,3.3 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:3.5 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.25 V
最小供电电压:1.15 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:40 mm

EP2S90F1508C5ES 数据手册

 浏览型号EP2S90F1508C5ES的Datasheet PDF文件第2页浏览型号EP2S90F1508C5ES的Datasheet PDF文件第3页浏览型号EP2S90F1508C5ES的Datasheet PDF文件第4页浏览型号EP2S90F1508C5ES的Datasheet PDF文件第6页浏览型号EP2S90F1508C5ES的Datasheet PDF文件第7页浏览型号EP2S90F1508C5ES的Datasheet PDF文件第8页 
Contents  
Contents  
Timing Model ....................................................................................................................................... 5–20  
Preliminary & Final Timing .......................................................................................................... 5–20  
I/O Timing Measurement Methodology .................................................................................... 5–21  
Performance .................................................................................................................................... 5–27  
Internal Timing Parameters .......................................................................................................... 5–34  
Stratix II Clock Timing Parameters .............................................................................................. 5–41  
Clock Network Skew Adders ....................................................................................................... 5–50  
IOE Programmable Delay ............................................................................................................. 5–51  
Default Capacitive Loading of Different I/O Standards .......................................................... 5–52  
I/O Delays ....................................................................................................................................... 5–54  
Maximum Input & Output Clock Toggle Rate .......................................................................... 5–66  
Duty Cycle Distortion ......................................................................................................................... 5–77  
DCD Measurement Techniques ................................................................................................... 5–78  
High-Speed I/O Specifications .......................................................................................................... 5–87  
PLL Timing Specifications .................................................................................................................. 5–91  
External Memory Interface Specifications ....................................................................................... 5–94  
JTAG Timing Specifications ............................................................................................................... 5–96  
Document Revision History ............................................................................................................... 5–97  
Chapter 6. Reference & Ordering Information  
Software .................................................................................................................................................. 6–1  
Device Pin-Outs ..................................................................................................................................... 6–1  
Ordering Information ........................................................................................................................... 6–1  
Document Revision History ................................................................................................................. 6–2  
Altera Corporation  
v

与EP2S90F1508C5ES相关器件

型号 品牌 描述 获取价格 数据表
EP2S90F1508I3ES ALTERA Stratix II Device Handbook, Volume 1

获取价格

EP2S90F1508I4 INTEL Field Programmable Gate Array, 36384 CLBs, 717MHz, 90960-Cell, CMOS, PBGA1508, 40 X 40 MM,

获取价格

EP2S90F1508I4ES ALTERA Stratix II Device Handbook, Volume 1

获取价格

EP2S90F1508I4N INTEL Field Programmable Gate Array, 4548 CLBs, 717MHz, 90960-Cell, CMOS, PBGA1508, 40 X 40 MM,

获取价格

EP2S90F1508I5ES ALTERA Stratix II Device Handbook, Volume 1

获取价格

EP2S90F780C4N ALTERA Field Programmable Gate Array, 4548 CLBs, 717MHz, 90960-Cell, CMOS, PBGA780, 29 X 29 MM, 1

获取价格

EP2S90F780C5 INTEL Field Programmable Gate Array, 36384 CLBs, 640MHz, 90960-Cell, CMOS, PBGA780, 29 X 29 MM,

获取价格

EP2S90F780C5N ALTERA Field Programmable Gate Array, 4548 CLBs, 640MHz, 90960-Cell, CMOS, PBGA780, 29 X 29 MM, 1

获取价格

EP2S90H1508C3ES ALTERA Stratix II Device Handbook, Volume 1

获取价格

EP2S90H1508C4ES ALTERA Stratix II Device Handbook, Volume 1

获取价格

EP2S90H1508C5ES ALTERA Stratix II Device Handbook, Volume 1

获取价格

EP2S90H1508I3ES ALTERA Stratix II Device Handbook, Volume 1

获取价格

EP2S90H1508I4ES ALTERA Stratix II Device Handbook, Volume 1

获取价格

EP2S90H1508I5ES ALTERA Stratix II Device Handbook, Volume 1

获取价格

EP2S90H484I4N INTEL Field Programmable Gate Array, 90960-Cell, CMOS, PBGA484,

获取价格

EP2S-B3G1 NEC LOW SOUND PRESSURE

获取价格

EP2S-B3G1T NEC LOW SOUND PRESSURE

获取价格

EP2S-B3G1TT NEC LOW SOUND PRESSURE

获取价格

EP2S-B3G2 NEC LOW SOUND PRESSURE

获取价格

EP2S-B3G2T NEC LOW SOUND PRESSURE

获取价格