Datasheet > EP20K200ERC208-3X

EP20K200ERC208-3X

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
116页	1588K
描述
Loadable PLD, CMOS, PQFP208, 30.40 X 30.40 MM, 0.50 MM PITCH, RQFP-208

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APEX 20K Programmable Logic Device Family Data Sheet

■

Flexible clock management circuitry with up to four phase-locked

loops (PLLs)

–

Built-in low-skew clock tree

Up to eight global clock signals

ClockLock^TMfeature reducing clock delay and skew

ClockBoost^TMfeature providing clock multiplication and

division

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ClockShift^TMprogrammable clock phase and delay shifting

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Powerful I/ O features

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Compliant with peripheral component interconnect Special

Interest Group (PCI SIG) PCI Local Bus Specification,

Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits

Support for high-speed external memories, including DDR

SDRAM and ZBT SRAM (ZBT is a trademark of Integrated

Device Technology, Inc.)

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Bidirectional I/ O performance (t_CO+ t_SU) up to 250 MHz

LVDS performance up to 840 Mbits per channel

Direct connection from I/ O pins to local interconnect providing

fast t_COand t_SUtimes for complex logic

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MultiVolt I/ O interface support to interface with 1.8-V, 2.5-V,

3.3-V, and 5.0-V devices (see Table 3)

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Programmable clamp to V_CCIO

Individual tri-state output enable control for each pin

Programmable output slew-rate control to reduce switching

noise

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Support for advanced I/ O standards, including low-voltage

differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-

series terminated logic (SSTL-3 and SSTL-2), Gunning

transceiver logic plus (GTL+), and high-speed terminated logic

(HSTL Class I)

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Pull-up on I/ O pins before and during configuration

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Advanced interconnect structure

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Four-level hierarchical FastTrack^®Interconnect structure

providing fast, predictable interconnect delays

Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by

software tools and megafunctions)

–

Dedicated cascade chain that implements high-speed,

high-fan-in logic functions (automatically used by software tools

and megafunctions)

Interleaved local interconnect allows one LE to drive 29 other

LEs through the fast local interconnect

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Advanced packaging options

–

Available in a variety of packages with 144 to 1,020 pins (see

Tables 4 through 7)

FineLine BGA^TMpackages maximize board space efficiency

–

Advanced software support

–

Software design support and automatic place-and-route

provided by the Altera^®Quartus^TMII development system for

Altera Corporation

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