Datasheet > EN80C251SB16

EN80C251SB16

更新时间： 2024-10-01 20:08:55

品牌	Logo	应用领域
英特尔 - INTEL		微控制器
页数	文件大小	规格书
36页	257K
描述
Microcontroller, 8-Bit, 80251 CPU, 16MHz, CMOS, PQCC44

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中文翻译

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技术参数
数据手册
替代型号

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EN80C251SB16 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	QCCJ, LDCC44,.7SQ	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.31.00.01
风险等级：	5.79	位大小：	8
CPU系列：	80251	JESD-30 代码：	S-PQCC-J44
端子数量：	44	最高工作温度：	25 °C
最低工作温度：	25 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	5 V	认证状态：	Not Qualified
RAM（字节）：	1024	ROM（单词）：	0
速度：	16 MHz	子类别：	Microcontrollers
最大压摆率：	80 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
Base Number Matches：	1

EN80C251SB16 数据手册

PRELIMINARY

8XC251SA/SB/SP/SQ

HIGH-PERFORMANCE

CHMOS MICROCONTROLLER

Commercial/Express

■ Real-time and Programmed Wait State

Bus Operation

■ User-selectable Configurations:

— External Wait States (0-3 wait states)

— Address Range & Memory Mapping

— Page Mode

■ Binary-code Compatible with MCS 51

■ Pin Compatible with 44-pin PLCC and 40-

pin PDIP MCS 51 Sockets

■ 32 Programmable I/O Lines

■ Register-based MCS 251 Architecture

■ Seven Maskable Interrupt Sources

with Four Programmable Priority

Levels

— 40-byte Register File

— Registers Accessible as Bytes, Words,

or Double Words

■ Three Flexible 16-bit Timer/counters

■ Hardware Watchdog Timer

■ Programmable Counter Array

— High-speed Output

■ Enriched MCS 51 Instruction Set

— 16-bit and 32-bit Arithmetic and Logic

Instructions

— Compare and Conditional Jump

Instructions

— Compare/Capture Operation

— Pulse Width Modulator

— Expanded Set of Move Instructions

— Watchdog Timer

■ Linear Addressing

■ Programmable Serial I/O Port

— Framing Error Detection

■ 256-Kbyte Expanded External Code/Data

Memory Space

■ ROM/OTPROM/EPROM Options:

16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or

without ROM/OTPROM/EPROM

— Automatic Address Recognition

■ High-performance CHMOS Technology

■ Static Standby to 16-MHz Operation

■ 16-bit Internal Code Fetch

■ Complete System Development

■ 64-Kbyte Extended Stack Space

Support

■ On-chip Data RAM Options:

— Compatible with Existing Tools

1-Kbyte (SA/SB) or 512-Byte (SP/SQ)

— New MCS 251 Tools Available:

■ 8-bit, 2-clock External Code Fetch in

Compiler, Assembler, Debugger, ICE

Page Mode

■ Fast MCS 251 Instruction Pipeline

■ Package Options (PDIP, PLCC, and

Ceramic DIP)

A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code

compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51

microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and

efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is

available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.

A variety of features can be selected by new user-programmable configurations.

May 1996

Order Number: 272783-003

12 3 4 5 6 7...36

中文翻译

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EN80C251SB16 替代型号

型号	品牌	替代类型	描述	数据表
TN80C251SB16	INTEL	类似代替	HIGH-PERFORMANCE CHMOS MICROCONTROLLER

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