EN29F040A-55PI PDF预览

EN29F040A-55PI

更新时间: 2025-07-28 06:57:15
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页数 文件大小 规格书
35页 272K
描述
4 Megabit (512K x 8-bit) Flash Memory

EN29F040A-55PI 数据手册

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EN29F040A  
EN29F040A  
4 Megabit (512K x 8-bit) Flash Memory  
FEATURES  
JEDEC Standard program and erase  
commands  
5.0V operation for read/write/erase  
operations  
JEDEC standard  
polling and toggle  
DATA  
Fast Read Access Time  
bits feature  
- 45ns, 55ns, 70ns, and 90ns  
Single Sector and Chip Erase  
Sector Unprotect Mode  
Sector Architecture:  
- 8 uniform sectors of 64Kbytes each  
- Supports full chip erase  
Embedded Erase and Program Algorithms  
- Individual sector erase supported  
- Sector protection:  
Hardware locking of sectors to prevent  
program or erase operations within  
individual sectors  
Erase Suspend / Resume modes:  
Read and program another Sector during  
Erase Suspend Mode  
0.23 µm triple-metal double-poly  
triple-well CMOS Flash Technology  
High performance program/erase speed  
- Byte program time: 10µs typical  
- Sector erase time: 500ms typical  
- Chip erase time: 3.5s typical  
Low Vcc write inhibit < 3.2V  
100K endurance cycle  
Package Options  
- 32-pin PDIP  
Low Standby Current  
- 1µA CMOS standby current-typical  
- 1mA TTL standby current  
- 32-pin PLCC  
Low Power Active Current  
- 30mA active read current  
- 30mA program/erase current  
- 32-pin TSOP (Type 1)  
Commercial and Industrial Temperature  
Ranges  
GENERAL DESCRIPTION  
The EN29F040A is a 4-Megabit, electrically erasable, read/write non-volatile flash memory.  
Organized into 512K words with 8 bits per word, the 4M of memory is arranged in eight uniform  
sectors of 64Kbytes each. Any byte can be programmed typically in 10µs. The EN29F040A  
features 5.0V voltage read and write operation, with access times as fast as 45ns to eliminate the  
need for WAIT states in high-performance microprocessor systems.  
The EN29F040A has separate Output Enable (  
), Chip Enable (  
), and Write Enable (  
)
W E  
OE  
CE  
controls, which eliminate bus contention issues. This device is designed to allow either single (or  
multiple) Sector or full chip erase operation, where each Sector can be individually protected against  
program/erase operations or temporarily unprotected to erase or program. The device can sustain a  
minimum of 100K program/erase cycles on each Sector.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2003 Eon Silicon Solution, Inc., www.essi.com.tw  
Rev. B, Issue Date: 2004/04/01  
1

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