EM8632
Functional Description
UVLO
An UVLO comparator is implemented in EM8632 to
monitor the VDD pin voltage. As shown in Fig. 11, a
hysteresis is built in to prevent the shutdown from
the voltage drop during startup. The UVLO (on) and
UVLO (off) are setting at 15V and 9.8V,
respectively.
Fig. 12
Switching Frequency
To guarantee accurate frequency, EM8632 is
trimmed to 5% tolerance. The internal oscillator
also generates slope compensation, 75% maximum
duty limit. Connect a resistor form RT pin to GND
according to equation below to program the
switching frequency:
Fig. 11
Startup Operation
Fig. 12 shows a typical startup circuit and
transformer auxiliary winding for the EM8632
application, it consumes only startup current
(typical 6uA) and the current supplied through the
startup resistor charges the VDD capacitor (CVDD).
When VDD reaches UVLO (on) voltage, EM8632
begins switching and the current consumed
increases to 2mA. Then, the power required is
supplied from the transformer auxiliary winding.
The hysteresis of UVLO (off) provides more holdup
time, which allows using a small capacitor for VDD.
The ultra low startup current (typical 6uA) allow
system using higher resistance value of RStart. It
provides a fast startup and low power dissipation
solution.
fsw (KHz)= 6500/RT(KΩ)
Leading Edge Blanking (LEB)
Each time the power MOSFET turn on, the MOSFET
COSS, secondary rectifier reverse recovery current
and gate driver sourcing current comprise the
current spike. To avoid premature termination of
the switching pulse, a leading edge blanking time is
built in. During the blanking time (300nS), the
PWM comparator is off and cannot switch off the
gate driver. It is recommended to adopt a smaller
R-C filter (as show ad Fig.13) for high power
application to avoid the total spike width over
300nS leading edge blanking time.
2013/01/30
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