Datasheet > EM720FP16AS-70L

EM720FP16AS-70L

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
EMLSI		/
页数	文件大小	规格书
11页	188K
描述
128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM

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中文翻译

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数据手册

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EM720FP16AS-70L 数据手册

EM610FV8T Series

merging Memory & Logic Solutions Inc.

Low Power, 128Kx8 SRAM

V_TM

AC OPERATING CONDITIONS

Test Conditions (Test Load and Test Input/Output Reference)

R₁

Input Pulse Level : 0.4 to 2.2V

Input Rise and Fall Time : 5ns

Input and Output reference Voltage : 1.5V

Output Load (See right) : CL = 100pF+ 1 TTL

R₂

CL¹⁾

CL¹⁾= 30pF + 1 TTL

1. Including scope and Jig capacitance

2. R₁=3070W,

R₂=3150W

3. V_TM=2.8V

READ CYCLE (V_cc=2.7 to 3.6V, Gnd = 0V, T_A= -40^oC to +85^oC)

55ns

70ns

Unit

Symbol

Parameter

Read cycle time

Min

Max

Min

Max

t_RC

t_AA

t_co1,t_co2

t_OE

t_LZ1,t_LZ2

t_OLZ

t_HZ1,t_HZ2

t_OHZ

Address access time

Chip select to output

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

t_OH

WRITE CYCLE (V_cc=2.7 to 3.6V, Gnd = 0V, T_A= -40^oC to +85^oC)

55ns

70ns

Unit

Symbol

Parameter

Write cycle time

Min

Max

Min

Max

t_WC

t_CW1,t_CW2

t_As

Chip select to end of write

Address setup time

Address valid to end of write

Write pulse width

t_AW

t_WP

Write recovery time

t_WR

Write to ouput high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

t_WHZ

t_DW

t_DH

t_OW

1 2 3 456 7 8...11

中文翻译

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