EM7180SFP
3.3. Host I2C Interface (Host Bus)
The host will control SFP on the host bus via SENtral’s I2C host interface. The host interface consists of 2 wires: the serial
clock, SCLS, and the serial data line, SDAS. Both lines are bi-directional. SENtral is connected to the host bus via the SDAS
and SCLS pins, which incorporate open drain drivers within the device. The host bus lines must be externally connected to a
positive supply voltage (Vdd) via a pull-up resistor. See Section “I2C Pull-Up Resistance” for more on the pull-up resistor.
SENtral’s 7-bit I2C slave address is 0b010100x, where the most significant 6 bits of the slave address are pre-defined in
hardware and are the same for all SENtral devices. The least significant bit is user-configurable, using the SA0 pin to set the bit
to ‘0’ or ‘1’. For example, grounding the SA0 pin (‘0’ value) results in the 7-bit address of 0b0101000. This should be set so the
SENtral slave address is unique to any other devices on the host bus.
Data transfer is always initiated by the host. Data is transferred between the host and SENtral serially through the data line
(SDAS) in an 8-bit transfer format. The transfer is synchronized by the serial clock line, SCLS. Supported transfer formats are
single-byte read, multiple-byte read, single-byte write, and multiple-byte write. SENtral as part of SFP is not utilizing clock
stretching feature of I2C bus and SCLS is driven by the Host MCU only.
Host I2C Transfer formats
Fig. 8 illustrates writing data to registers in single-byte or multiple-byte mode.
START
S
SLAVE ADDRESS
RW ACK REGISTER ADDRESS (N) ACK DATA TO REGISTER (N) ACK DATA TO REGISTER (N+1) ACK STOP
R7R6 R5 R4 R3 R2 R1 R0 D7D6 D5 D4 D3 D2 D1 D0 D7D6 D5 D4 D3 D2 D1 D0
A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
P
From Host to SENtral
From SENtral to Host
------------ Data Transferred (n bytes + acknowledge) ------------
Fig. 8 I2C Slave Write Example
The I2C host interface supports both a read sequence using repeated START conditions, shown in Fig. 9, and a sequence in
which the register address is sent in a separate sequence than the data, shown in Fig. 10 and Fig. 11.
START
S
SLAVE ADDRESS
RW ACK REGISTER ADDRESS (N) ACK START
R7 R6 R5 R4 R3 R2 R1 R0 SR
SLAVE ADDRESS
RW ACK DATA FROM REGISTER (N) NACK STOP
A6 A5 A4 A3 A2 A1 A0
0
0
0
A6 A5 A4 A3 A2 A1 A0
1
0
D7 D6
D5 D4 D3 D2 D1 D0
1
P
Data Transferred
(n bytes + acknowledge)
Fig. 9 I2C Slave Read Example, with Repeated START
START
SLAVE ADDRESS
A6 A5 A4 A3 A2 A1 A0
RW ACK
REGISTER ADDRESS (N)
ACK STOP
S
0
0
R7 R6 R5 R4 R3 R2 R1 R0
0
P
Fig. 10 I2C Slave Write Register Address Only
START
S
SLAVE ADDRESS
RW ACK
DATA FROM REG. (N)
ACK DATA FROM REG. (N+1) NACK STOP
D7D6 D5 D4 D3 D2 D1 D0
A6 A5 A4 A3 A2 A1 A0
1
0
D7D6 D5 D4 D3 D2 D1 D0
0
1
P
From Host to SENtral
From SENtral to Host
-------------- Data Transferred (n bytes + acknowledge) --------------
Fig. 11 I2C Slave read register from current address
12
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Copyright 2014, EM Microelectronic-Marin SA
7180SFP-DS Version 1.1, 10-Dec-14
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