EL7158
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
EL7158 drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below
Applications Information
Product Description
The EL7158 is a high performance 40MHz pin driver. It
contains two analog switches connecting V and V to OUT.
Depending on the value of the IN pin, one of the two
switches will be closed and the other switch open. An output
enable (OE) is also supplied which opens both switches
simultaneously.
H
L
T
(125°C). It is necessary to calculate the power
JMAX
dissipation for a given application prior to selecting the
package type.
Power dissipation may be calculated:
Due to the topology of the EL7158, both the V and V pins
H
L
2
2
PD = (V × I ) + (C
× V × f) + (C × V
× f)
OUT
can be connected to any voltage between the V + and V -
S
S
S
S
INT
S
L
pins, but V must be greater than V in order to prevent
H
L
where:
turning on the body diode at the output stage.
V is the total power supply to the EL7158 (from V + to
Three-State Operation
S
S
GND)
When the OE pin is low, the output is three-state (floating.)
The output voltage is the parasitic capacitance’s voltage. It
can be any voltage between V and V , depending on the
V
is the swing on the output (V - V )
H L
OUT
C is the load capacitance
H
L
L
previous state. At three-state, the output voltage can be
C
is the internal load capacitance (100pF max)
INT
is the quiescent supply current (3mA max)
pushed to any voltage between V and V . The output
H
L
I
S
voltage can’t be pushed higher than V or lower than V
H
L
f is frequency
since the body diode at the output stage will turn on.
Having obtained the application’s power dissipation, a
maximum package thermal coefficient may be determined,
Supply Voltage Range and Input Compatibility
The EL7158 is designed for operation on supplies from 5V to
18V (4.5V to 18V maximum). Table 2 shows the
to maintain the internal die temperature below T
:
JMAX
T
– T
MAX
PD
JMAX
specifications for the relationship between the V +, V -, V ,
S
S
H
θ
= ----------------------------------------
JA
V , and GND pins.
L
where:
All input pins are compatible with both 3V and 5V CMOS
signals. With a positive supply (V +) of 5V, the EL7158 is
S
T
T
is the maximum junction temperature (125°C)
JMAX
is the maximum operating temperature
also compatible with TTL inputs.
MAX
Power Supply Bypassing
PD is the power dissipation calculated above
When using the EL7158, it is very important to use adequate
power supply bypassing. The high switching currents
developed by the EL7158 necessitate the use of a bypass
θ
thermal resistance on junction to ambient
JA
is 160°C/W for the SO8 package when using a standard
θ
JA
JEDEC JESD51-3 single-layer test board. If T
is
JMAX
capacitor between the supplies (V + & V -) and GND pins.
S
S
greater than 125°C when calculated using the equation
above, then one of the following actions must be taken:
It is recommended that a 2.2µF tantalum capacitor be used
in parallel with a 0.1µF low-inductance ceramic MLC
capacitor. These should be placed as close to the supply
Reduce θ the system by designing more heat-sinking
into the PCB (as compared to the standard JEDEC
JESD51-3)
JA
pins as possible. It is also recommended that the V and V
pins have some level of bypassing, especially if the EL7158
is driving highly capacitive loads.
H
L
De-rate the application either by reducing the switching
frequency, the capacitive load, or the maximum operating
(ambient) temperature (T
)
MAX
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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