Datasheet > EI16C550

EI16C550

更新时间： 2022-11-25 09:30:02

品牌	Logo	应用领域
IMP		先进先出芯片
页数	文件大小	规格书
2页	47K
描述
FIFO UART

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数据手册

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EI16C550 数据手册

Ei16C550

FIFO UART

Semiconductor, Inc.

The UART includes a programmable baud generator

which is capable of dividing the timing reference clock

input by divisors of 1 to (2¹⁶-1), and producing a 16 x

clock to drive the receiver logic. Also included in the

UART is a complete MODEM control capability, and

processor interrupt system that may be software tai-

lored to the users requirement to minimize the com-

puting needed to handle the communications link.

BLOCK DIAGRAM

RECEIVER

SHIFT

INTERNAL

DATA BUS

(10)

RECEIVER

BUFFER

SIN

DATA

BUS

BUFFER

(1-8)

D7-D0

LINE

CONTROL

RECEIVER

TIMING

(9)

RCLK

(28)

(27)

(26)

(12)

(13)

(14)

(25)

(35)

(22)

(21)

(19)

(18)

(23)

(24)

(16)

(17)

(29)

DIVISOR

LATCH

(LS)

CS0

CS1

CS2•

ADR

CONTROL

BAUD

GENERATOR

(15)

DIVISOR

LATCH

(MS

BAUDOUT

TRANSMITTER

TIMING

SELECT

LINE

STATUS

AND

CONTROL

LOGIC

DISTR

DISTR•

DOSTR

DOSTR•

DDIS

TXRDY•

XTAL1

CONTROL

FIFO

(11)

TRANSMITTER

SHIFT

SOUT

MODEM

CONTROL

XTAL2

RXRDY•

(32)

(36)

(33)

(37)

(38)

(39)

RTS•

CTS•

DTR•

DSR•

DCD•

MODEM

STATUS

MODEM

CONTROL

LOGIC

INTERRUPT

ENABLE

•

INTERRUPT

CONTROL

LOGIC

(40)

(20)

(34)

(31)

POWER

SUPPLY

3.3, 5V

GND

OUT1•

OUT2•

INTERRUPT

(30)

INTRPT

FIFO

CONTROL

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