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EFM32GG232 PDF预览

EFM32GG232

更新时间: 2022-02-26 12:28:54
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芯科 - SILICON /
页数 文件大小 规格书
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描述
High Performance 32-bit processor

EFM32GG232 数据手册

 浏览型号EFM32GG232的Datasheet PDF文件第4页浏览型号EFM32GG232的Datasheet PDF文件第5页浏览型号EFM32GG232的Datasheet PDF文件第6页浏览型号EFM32GG232的Datasheet PDF文件第8页浏览型号EFM32GG232的Datasheet PDF文件第9页浏览型号EFM32GG232的Datasheet PDF文件第10页 
...the world's most energy friendly microcontrollers  
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit  
operations are not supported.  
2.1.27 General Purpose Input/Output (GPIO)  
In the EFM32GG232, there are 53 General Purpose Input/Output (GPIO) pins, which are divided into  
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More  
advanced configurations like open-drain, filtering and drive strength can also be configured individually  
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM  
outputs or USART communication, which can be routed to several locations on the device. The GPIO  
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the  
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other  
peripherals.  
2.2 Configuration Summary  
The features of the EFM32GG232 is a subset of the feature set described in the EFM32GG Reference  
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.  
Table 2.1. Configuration Summary  
Module  
Cortex-M3  
DBG  
Configuration  
Pin Connections  
Full configuration  
Full configuration  
NA  
DBG_SWCLK, DBG_SWDIO,  
DBG_SWO  
MSC  
Full configuration  
Full configuration  
Full configuration  
Full configuration  
Full configuration  
Full configuration  
Full configuration  
Full configuration  
Full configuration  
Full configuration with IrDA  
Full configuration with I2S  
Full configuration with I2S  
Full configuration  
Full configuration  
Full configuration with DTI  
Full configuration  
Full configuration  
Full configuration  
Full configuration  
Full configuration  
Full configuration  
NA  
DMA  
NA  
RMU  
NA  
EMU  
NA  
CMU  
CMU_OUT0, CMU_OUT1  
NA  
WDOG  
PRS  
NA  
I2C0  
I2C0_SDA, I2C0_SCL  
I2C1_SDA, I2C1_SCL  
US0_TX, US0_RX. US0_CLK, US0_CS  
US1_TX, US1_RX, US1_CLK, US1_CS  
US2_TX, US2_RX, US2_CLK, US2_CS  
LEU0_TX, LEU0_RX  
LEU1_TX, LEU1_RX  
TIM0_CC[2:0], TIM0_CDTI[2:0]  
TIM1_CC[2:0]  
I2C1  
USART0  
USART1  
USART2  
LEUART0  
LEUART1  
TIMER0  
TIMER1  
TIMER2  
TIMER3  
RTC  
TIM2_CC[2:0]  
TIM3_CC[2:0]  
NA  
BURTC  
LETIMER0  
NA  
LET0_O[1:0]  
www.silabs.com  
2016-03-21 - EFM32GG232FXX - d0125_Rev1.40  
7
 
 

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