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EDI88128C85CI PDF预览

EDI88128C85CI

更新时间: 2024-01-16 16:38:17
品牌 Logo 应用领域
WEDC 静态存储器内存集成电路
页数 文件大小 规格书
8页 387K
描述
Standard SRAM, 128KX8, 85ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

EDI88128C85CI 技术参数

是否Rohs认证: 不符合生命周期:Transferred
Reach Compliance Code:unknown风险等级:5.89
最长访问时间:85 ns其他特性:AUTOMATIC POWER-DOWN
I/O 类型:COMMONJESD-30 代码:R-CDIP-T32
JESD-609代码:e0内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端口数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX8输出特性:3-STATE
可输出:YES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP32,.6
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified最大待机电流:0.005 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.095 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL

EDI88128C85CI 数据手册

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EDI88128C  
White Electronic Designs  
128Kx8 MONOLITHIC SRAM, SMD 5962-89598  
The EDI88128C is a high speed, high performance,  
Monolithic CMOS Static RAM organized as 128Kx8.  
FEATURES  
Access Times of 70, 85, 100ns  
The device is also available as EDI88130C with an  
additional chip select line (CS2) which will automatically  
power down the device when proper logic levels are  
applied.  
Available with Single Chip Selects (EDI88128) or  
Dual Chip Selects (EDI88130)  
2V Data Retention (LP Versions)  
CS# and OE# Functions for Bus Control  
TTL Compatible Inputs and Outputs  
Fully Static, No Clocks  
The second chip select line (CS2) can be used to provide  
system memory security during power down in non-battery  
backed up systems and simplifiy decoding schemes in  
memory banking where large multiple pages of memory  
are required.  
Organized as 128Kx8  
Industrial, Military and Commercial Temperature  
Ranges  
The EDI88128C and the EDI88130C have eight bi-  
directional input-output lines to provide simultaneous  
access to all bits in a word. An automatic power down  
feature permits the on-chip circuitry to enter a very low  
standby mode and be brought back into operation at a  
speed equal to the address access time.  
Thru-hole and Surface Mount Packages JEDEC  
Pinout  
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)  
• 32 lead Ceramic SOJ (Package 140)  
Single +5V ( 10ꢀ) Supply Operation  
Low power versions, EDI88128LP and EDI88130LP, offer  
a 2V data retention function for battery back-up opperation.  
Military product is available compliant to Appendix A of  
MIL-PRF-38535.  
FIGURE 1 – PIN CONFIGURATION  
PIN DESCRIPTION  
I/O0-7  
A0-16  
WE#  
Data Inputs/Outputs  
Address Inputs  
Write Enable  
32 DIP  
32 SOJ  
CS1#, CS2  
OE#  
VCC  
VSS  
NC  
Chip Selects  
Top View  
Output Enable  
Power (+5V 10ꢀ%  
Ground  
NC  
A16  
A14  
A12  
A7  
1
2
3
4
5
6
7
8
9
32 VCC  
31 A15  
30 NC/CS2*  
29 WE#  
28 A13  
27 A8  
Not Connected  
A6  
A5  
26 A9  
BLOCK DIAGRAM  
A4  
25 A11  
24 OE#  
23 A10  
22 CS1#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
A3  
A2 10  
A1 11  
AØ 12  
I/OØ 13  
I/O1 14  
I/O2 15  
VSS 16  
WE#  
CS1#  
CS2  
OE#  
* Pin 30 is NC for 88128 or CS2 for 88130.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
April 2005  
Rev. 17  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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