EBE21AE8ACFA
Block Diagram
/RCS1
/RCS0
R
S
R
S
/DQS4
DQS4
/DQS0
DQS0
R
S
R
S
R
S
R
NU/
NU/
S
/CS DQS /DQS
/CS DQS /DQS
NU/
NU/
/CS DQS /DQS
/CS DQS /DQS
/DQS13
/RDQS
/RDQS
/DQS9
/RDQS
/RDQS
R
S
S
R
DM,
RDQS
DM,
RDQS
S
S
DM/
RDQS
DM/
RDQS
DM4/DQS13
DM0/DQS9
D4
D13
D0
D9
8
R
8
DQ0
to DQ7
DQ0
to DQ7
R
DQ0
to DQ7
DQ0
to DQ7
DQ32 to DQ39
/DQS5
DQ0 to DQ7
/DQS1
R
R
S
R
R
S
S
S
DQS5
/DQS14
DQS1
/DQS10
R
S
R
S
NU/
/RDQS
DM/
/RDQS
NU/
/CS DQS /DQS
/CS DQS /DQS
NU/
/RDQS
DM/
RDQS
NU/
/RDQS
DM/
RDQS
/CS DQS /DQS
/CS DQS /DQS
/RDQS
DM/
R
R
S
R
R
S
DM5/DQS14
DQ40 to DQ47
/RDQS
D5
D14
DM1/DQS10
DQ8 to DQ15
D1
D10
8
S
8
S
DQ0
to DQ7
DQ0
to DQ7
DQ0
to DQ7
DQ0
to DQ7
R
S
R
S
/DQS6
DQS6
/DQS2
DQS2
R
S
R
S
R
S
R
NU/
NU/
S
/CSDQS /DQS
/CSDQS /DQS
NU/
NU/
/CS DQS /DQS
/CS DQS /DQS
/DQS15
/RDQS
/RDQS
/DQS11
/RDQS
/RDQS
R
S
R
S
DM/
/RDQS
DM/
/RDQS
DM/
RDQS
DM/
RDQS
DM6/DQS15
DM2/DQS11
D6
D15
D2
D11
8
R
S
8
DQ0
to DQ7
DQ0
to DQ7
R
S1
DQ0
to DQ7
DQ0
to DQ7
DQ48 to DQ55
/DQS7
DQ16 to DQ23
/DQS3
R
R
S
R
R
S
S
S
DQS7
/DQS16
DQS3
/DQS12
R
S
R
S
NU/
/RDQS
DM/
/RDQS
NU/
/CSDQS /DQS
/CSDQS /DQS
NU/
/RDQS
DM/
RDQS
NU/
/RDQS
DM/
RDQS
/CS DQS /DQS
/CS DQS /DQS
/RDQS
DM/
R
R
S
R
R
S
DM7/DQS16
DQ56 to DQ63
/RDQS
D7
D16
DM3/DQS12
DQ24 to DQ31
D3
D12
8
S
8
S
DQ0
to DQ7
DQ0
to DQ7
DQ0
to DQ7
DQ0
to DQ7
R
S
/DQS8
R
S
DQS8
/DQS17
R
S
NU/
NU/
/CS DQS /DQS
/CS DQS /DQS
/RDQS
/RDQS
R
R
S
DM/
/RDQS
DM/
/RDQS
DM8/DQS17
CB0 to CB7
D8
D17
8
S
DQ0
to DQ7
DQ0
to DQ7
Serial PD
SCL
R
S
S
S
S
S
S
S
S
2
/CS0*
/RCS0 -> /CS: SDRAMs D0 to D8
/RCS1 -> /CS: SDRAMs D9 to D17
D0 to D17: 1G bits DDR2 SDRAM
U0: 2k bits EEPROM
RS: 22Ω
PLL: CUA877
Register: SSTUB32866
SCL
SDA
R
SDA
2
/CS1*
U0
R
R
E
G
I
S
T
E
R
BA0 to BA2
RBA0 to RBA2 -> BA0 to BA2: SDRAMs D0 to D17
RA0 to RA13 -> A0 to A13: SDRAMs D0 to D17
/RRAS -> /RAS: SDRAMs D0 to D17
A1 A2
WP A0
R
A0 to A13
R
SA0 SA1 SA2
/RAS
R
/CAS
/RCAS -> /CAS: SDRAMs D0 to D17
R
CKE0
R
P
L
L
PCK0 to PCK6,PCK8,PCK9 -> CK: SDRAMs D0 to D17
/PCK0 to /PCK6,/PCK8,/PCK9 -> /CK: SDRAMs D0 to D17
CK0
/CK0
VDDSPD
VDD
Serial PD
RCKE0 -> CKE: SDRAMs D0 to D8
RCKE1 -> CKE: SDRAMs D9 to D17
/RWE -> /WE: SDRAMs D0 to D17
RODT0 -> ODT: SDRAMs D0 to D8
D0 to D17
D0 to D17
D0 to D17
CKE1
PCK7 -> CK: register
/PCK7 -> /CK: register
R
S
VREF
VSS
/RESET
/WE
/ODT0
/ODT1
/RESET*
OE
R
S
R
S
RODT1 -> ODT: SDRAMs D9 to D17
3
/RST
3
/PCK7
*
Signals for Address and Command Parity Function
3
PCK7*
Register B
Register A
VSS
VDD
VDD
VDD
C0
C1
C0
C1
Notes:
1. DQ wiring may be changed within a byte.
PPO
/QERR
PAR_IN
PAR_IN
PPO
2. /CS0 connects to /DCS on register1 and /CSR on register2.
/CS1 connects to /CSR on register1 and /DCS on register2.
3. /RESET, PCK7 and /PCK7 connect to all registers.
Other signals connect to one of two registers.
Par_In
/QERR
/Err_Out
100kΩ
Data Sheet E1199E10 (Ver. 1.0)
8