EBE20RE4ABFA-4A-E

更新时间： 2024-02-06 09:59:26

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
29页	240K
描述
2GB Registered DDR2 SDRAM DIMM

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EBE20RE4ABFA-4A-E 数据手册

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EBE20RE4ABFA

6. tJIT (cc) is defined as the absolute difference in clock period between two consecutive clock cycles:

tJIT (cc) = Max. of |tCK_j+1− tCK_j|

tJIT (cc) is defines the cycle to cycle jitter when the DLL is already locked. tJIT (cc, lck) uses the same

definition for cycle to cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not

subject to production test.

7. tERR (nper) is defined as the cumulative error across multiple consecutive cycles from tCK (avg).

tERR (nper) is not subject to production test.





tERR(nper) =

tCKj − n×tCK(avg))





∑

j =1





2 ≤ n ≤ 50 for tERR (nper)

8. These parameters are specified per their average values, however it is understood that the following

relationship between the average timing and the absolute instantaneous timing hold at all times.

(minimum and maximum of spec values are to be used for calculations in the table below.)

Parameter

Symbol

min.

max.

Unit

Absolute clock period

tCK (abs) tCK (avg) min. + tJIT (per) min. tCK (avg) max. + tJIT (per) max. ps

Absolute clock high pulse

width

tCH (avg) min. × tCK (avg) min. + tCH (avg) max. × tCK (avg) max.

tCH (abs)

tCL (abs)

tJIT (duty) min.

tCL (avg) min. × tCK (avg) min. + tCL (avg) max. × tCK (avg) max.

tJIT (duty) min. + tJIT (duty) max.

+ tJIT (duty) max.

Absolute clock low pulse

width

Example: For DDR2-667, tCH(abs) min. = ( 0.48 × 3000 ps ) - 125ps = 1315ps

Data Sheet E0873E40 (Ver. 4.0)

1...21 22 232425 26 27...29

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