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EBE20RE4AAFA PDF预览

EBE20RE4AAFA

更新时间: 2022-11-25 10:32:54
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
22页 187K
描述
2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)

EBE20RE4AAFA 数据手册

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EBE20RE4AAFA  
Pin Description  
Pin name  
Function  
Address input  
Row address  
Column address  
A0 to A13  
A0 to A13  
A0 to A9, A11  
A10 (AP)  
Auto precharge  
BA0, BA1, BA2  
Bank select address  
Data input/output  
DQ0 to DQ63  
CB0 to CB7  
Check bit (Data input/output)  
Row address strobe command  
Column address strobe command  
Write enable  
/RAS  
/CAS  
/WE  
/CS0  
Chip select  
CKE0  
Clock enable  
CK0  
Clock input  
/CK0  
Differential clock input  
Input and output data strobe  
Clock input for serial PD  
Data input/output for serial PD  
Serial address input  
DQS0 to DQS17, /DQS0 to /DQS17  
SCL  
SDA  
SA0 to SA2  
VDD  
Power for internal circuit  
Power for serial EEPROM  
Input reference voltage  
Ground  
VDDSPD  
VREF  
VSS  
ODT0  
/RESET  
NC  
ODT control  
Reset pin (forces register and PLL inputs low) *1  
No connection  
Note: 1. Reset pin is connected to both OE of PLL and reset to register.  
Data Sheet E0440E30 (Ver. 3.0)  
4

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