Datasheet > EBD52UC8AAFA

EBD52UC8AAFA

更新时间： 2022-12-22 00:38:55

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
18页	180K
描述
512MB Unbuffered DDR SDRAM DIMM

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EBD52UC8AAFA 数据手册

EBD52UC8AAFA

Parameter

Symbol

tRRD

min.

max

—

Unit

Notes

Active to active command period

Write recovery time

tWR

—

Auto precharge write recovery and precharge time

Internal write to Read command delay

Exit self refresh to non-read command

Exit self refresh to read command

Exit power down to any non-read command

Exit precharge power down to read command

Average periodic refresh interval

tDAL

—

tWTR

tXSNR

tXSRD

tXPNR

tXPRD

tREF

—

tCK

200

tCK

µs

—

7.8

Notes: 1 tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These

parameters are not referenced to a specific voltage level, but specify when the device output is no longer

driving (HZ), or begins driving (LZ).

2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for

this parameter, but system performance (bus turnaround) will degrade accordingly.

3. The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or

before this CK edge. A valid transition is defined as monotonic, and meeting the input slew rate

specifications of the device. When no writes were previously in progress on the bus, DQS will be

transitioning from High-Z to logic Low. If a previous write was in progress, DQS could be High, Low, or

transitioning from High to Low at this time, depending on tDQSS.

4. A maximum of eight auto refresh commands can be posted to any given DDR SDRAM device.

5. tXPRD should be 200 tCK in the condition of the unstable CK operation during the power down mode.

6. For command/address and CK and /CK slew rate ≥ 1.0V/ns

Data Sheet E0362E20 (Ver. 2.0)

1...9 10 111213 14 15...18

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