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EBD25UC8AKFA-5B PDF预览

EBD25UC8AKFA-5B

更新时间: 2024-01-09 06:04:47
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
19页 152K
描述
256MB Unbuffered DDR SDRAM DIMM (32M words X 64 bits, 1 Rank)

EBD25UC8AKFA-5B 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM184
针数:184Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84Is Samacsys:N
访问模式:SINGLE BANK PAGE BURST最长访问时间:0.7 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N184
内存密度:2147483648 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:184
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM184
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):260电源:2.6 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES子类别:DRAMs
最大压摆率:2.56 mA最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):2.6 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

EBD25UC8AKFA-5B 数据手册

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EBD25UC8AKFA-5  
-5B  
-5C  
Parameter  
Symbol  
tRFC  
min.  
max.  
min.  
max.  
Unit  
ns  
Notes  
Auto refresh to Active/Auto refresh  
command period  
70  
70  
Active to Read/Write delay  
Precharge to active command period  
Active to Autoprecharge delay  
Active to active command period  
Write recovery time  
tRCD  
tRP  
15  
18  
ns  
ns  
ns  
ns  
ns  
15  
18  
tRAP  
tRRD  
tWR  
tRCD min.  
tRCD min.  
10  
15  
10  
15  
Auto precharge write recovery and  
precharge time  
(tWR/tCK)+  
(tRP/tCK)  
(tWR/tCK)+  
(tRP/tCK)  
tDAL  
tCK  
13  
Internal write to Read command delay  
tWTR  
tREF  
2
2
tCK  
µs  
Average periodic refresh interval  
7.8  
7.8  
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,  
refer to the corresponding component data sheet.  
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal  
transition is defined to occur when the signal level crossing VTT.  
3. The timing reference level is VTT.  
4. Output valid window is defined to be the period between two successive transition of data out or DQS  
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.  
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The  
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage  
level, but specify when the device output stops driving.  
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This  
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins  
driving.  
7. Input valid windows is defined to be the period between two successive transition of data input or DQS  
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.  
8. The timing reference level is VREF.  
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific  
reference voltage to judge this transition is not given.  
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not  
assured.  
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these  
values are 10% of tCK.  
12. VDD is assumed to be 2.6V ± 0.1V. VDD power supply variation per cycle expected to be less than  
0.4V/400 cycle.  
13. tDAL = (tWR/tCK)+(tRP/tCK)  
For each of the terms above, if not already an integer, round to the next highest integer.  
Example: For –5C Speed at CL = 3, tCK = 5ns, tWR = 15ns and tRP= 18ns,  
tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4)  
tDAL = 7 clocks  
Preliminary Data Sheet E0353E30 (Ver. 3.0)  
13  

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