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EBD21RD4ADNA-7B-E

更新时间： 2024-01-06 12:40:09

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	198K
描述
2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks)

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EBD21RD4ADNA-7B-E 数据手册

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EBD21RD4ADNA-E

12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than

0.4V/400 cycle.

13. tDAL = (tWR/tCK)+(tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer.

Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,

tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)

tDAL = 5 clocks

Timing Parameter Measured in Clock Cycle for Registered DIMM

Number of clock cycle

tCK

6ns

7.5ns

Parameter

Symbol

min.

max.

—

min.

max.

—

Unit

tCK

Write to pre-charge command delay (same bank) tWPD

Read to pre-charge command delay (same bank) tRPD

4 + BL/2

BL/2

3 + BL/2

BL/2

—

Write to read command delay (to input all data)

Burst stop command to write command delay

(CL = 3)

(CL = 3.5)

Burst stop command to DQ High-Z

(CL = 3)

tWRD

tBSTW

tBSTZ

2 + BL/2

—

2 + BL/2

—

3.5

—

tCK

—

3.5

(CL = 3.5)

3.5

Read command to write command delay

(to output all data)

(CL = 3)

tRWD

—

2 + BL/2

—

tCK

(CL = 3.5)

Pre-charge command to High-Z

(CL = 3)

tRWD

tHZP

3 + BL/2

—

3 + BL/2

—

tCK

(CL = 3.5)

tHZP

tWCD

tWR

3.5

—

3.5

—

tCK

Write command to data in latency

Write recovery

—

command

tMRD

—

tCK

Self refresh exit to non-read command

Self refresh exit to read command

Power down entry

tSNR

200

—

200

—

tCK

tSRD

tPDEN

tPDEX

Power down exit to command input

—

Data Sheet E0606E10 (Ver. 1.0)

1...11 12 131415 16 17...19

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