Datasheet > EBD11UD8ADDA-E

EBD11UD8ADDA-E

更新时间： 2022-11-25 15:23:22

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	213K
描述
1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)

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数据手册

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EBD11UD8ADDA-E 数据手册

EBD11UD8ADDA-E

Byte No. Function described

Minimum row active to row active delay

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value

Comments

12ns

(tRRD)

30H

-6B

-7A, -7B

3CH

48H

50H

15ns

18ns

20ns

Minimum /RAS to /CAS delay (tRCD)

-6B

-7A, -7B

Minimum active to precharge time

(tRAS)

-6B

2AH

42ns

-7A, -7B

2DH

80H

45ns

Module rank density

512M bytes

Address and command setup time

before clock (tIS)

-6B

75H

90H

75H

0.75ns^*1

0.9ns*¹

0.75ns^*1

-7A, -7B

Address and command hold time after

clock (tIH)

-6B

-7A, -7B

90H

45H

50H

45H

0.9ns*¹

0.45ns^*1

0.5ns*¹

0.45ns^*1

Data input setup time before clock (tDS)

-6B

-7A, -7B

Data input hold time after clock (tDH)

-6B

-7A, -7B

50H

00H

0.5ns*¹

36 to 40 Superset information

Future use

Active command period (tRC)

3CH

41H

60ns^*1

65ns*¹

-6B

-7A, -7B

Auto refresh to active/

Auto refresh command cycle (tRFC)

-6B

48H

72ns^*1

-7A, -7B

4BH

30H

75ns*¹

12ns*¹

SDRAM tCK cycle max. (tCK max.)

Dout to DQS skew

-6B

-7A, -7B

Data hold skew (tQHS)

-6B

2DH

32H

55H

450ps^*1

500ps*¹

550ps^*1

-7A, -7B

75H

00H

750ps*¹

46 to 61 Superset information

Future use

SPD Revision

Checksum for bytes 0 to 62

-6B

42H

-7A

F9H

24H

7FH

FEH

00H

249

-7B

Manufacturer’s JEDEC ID code

Elpida Memory

67 to 71 Manufacturer’s JEDEC ID code

Data Sheet E0603E10 (Ver. 1.0)

1...3 4 567 8 9...19

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