Datasheet > EBD11UD8ADDA-E

EBD11UD8ADDA-E

更新时间： 2022-11-25 15:23:22

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	213K
描述
1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)

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EBD11UD8ADDA-E 数据手册

EBD11UD8ADDA-E

Serial PD Matrix

Byte No. Function described

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value

Comments

128 bytes

Number of bytes utilized by module

80H

08H

manufacturer

Total number of bytes in serial PD

256 bytes

device

Memory type

07H

0DH

0BH

02H

40H

00H

04H

DDR SDRAM

Number of row address

Number of column address

Number of DIMM ranks

Module data width

64 bits

Module data width continuation

Voltage interface level of this assembly

SSTL2.5V

DDR SDRAM cycle time, CL = X

-6B

-7A,-7B

SDRAM access from clock (tAC)

-6B

-7A, -7B

60H

75H

70H

CL = 2.5*¹

0.70ns*¹

75H

00H

0.75ns*¹

None

7.6µs

Self refresh

DIMM configuration type

Refresh rate/type

82H

Primary SDRAM width

08H

00H

× 8

Error checking SDRAM width

Not used

SDRAM device attributes:

Minimum clock delay back-to-back

column access

01H

1 CLK

SDRAM device attributes:

0EH

04H

2,4,8

Burst length supported

SDRAM device attributes: Number of

banks on SDRAM device

SDRAM device attributes: /CAS latency 0

0CH

01H

02H

20H

C0H

2, 2.5

SDRAM device attributes: /CS latency

SDRAM device attributes: /WE latency

SDRAM module attributes

Unbuffered

VDD ± 0.2V

SDRAM device attributes: General

Minimum clock cycle time at

CL = X –0.5

75H

A0H

70H

CL = 2*¹

-6B, -7A

-7B

Maximum data access time (tAC) from

clock at CL = X –0.5

-6B

0.70ns*¹

0.75ns*¹

-7A, -7B

75H

00H

25 to 26

Minimum row precharge time (tRP)

-6B

-7A, -7B

48H

50H

18ns

20ns

Data Sheet E0603E10 (Ver. 1.0)

1 2 3 456 7 8...19

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