Datasheet > DSN9NC52A271Q54B

DSN9NC52A271Q54B

更新时间： 2024-01-23 18:31:16

品牌	Logo	应用领域
村田 - MURATA		/
页数	文件大小	规格书
62页	472K
描述
Feed Through Capacitor, 1 Function(s), 100V, 7A,

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技术参数
数据手册

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DSN9NC52A271Q54B 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8504.50.80.00
风险等级：	5.84	Is Samacsys：	N
其他特性：	STRAIGHT LEAD TYPE	电容：	270 µF
滤波器类型：	FEED THROUGH CAPACITOR	安装类型：	THROUGH HOLE MOUNT
功能数量：	1	最高工作温度：	85 °C
最低工作温度：	-25 °C	包装方法：	BULK
额定电流：	7 A	额定电压：	100 V
Base Number Matches：	1

DSN9NC52A271Q54B 数据手册

MAX 7000 Programmable Logic Device Family Data Sheet

Table 2. MAX 7000S Device Features

Feature

EPM7032S

EPM7064S

EPM7128S

EPM7160S

EPM7192S

EPM7256S

Usable gates

Macrocells

600

1,250

2,500

128

3,200

160

3,750

192

5,000

256

Logic array

blocks

Maximum

100

104

124

164

user I/O pins

(ns)

2.9

3.4

2.5

3.4

7.5

4.1

7.5

3.9

(ns)

2.5

FSU

CO1

CNT

(ns)

3.2

3.9

4.7

(MHz)

175.4

147.1

149.3

125.0

128.2

■

Open-drain output option in MAX 7000S devices

Programmable macrocell flipflops with individual clear, preset,

clock, and clock enable controls

Programmable power-saving mode for a reduction of over 50% in

each macrocell

Configurable expander product-term distribution, allowing up to

32 product terms per macrocell

...and More

Features

■

44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic

pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat

pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages

Programmable security bit for protection of proprietary designs

3.3-V or 5.0-V operation

■

–

MultiVolt^TMI/ O interface operation, allowing devices to

interface with 3.3-V or 5.0-V devices (MultiVolt I/ O operation is

not available in 44-pin packages)

–

Pin compatible with low-voltage MAX 7000A and MAX 7000B

devices

■

Enhanced features available in MAX 7000E and MAX 7000S devices

–

Six pin- or logic-driven output enable signals

Two global clock signals with optional inversion

Enhanced interconnect resources for improved routability

Fast input setup times provided by a dedicated path from I/ O

pin to macrocell registers

–

Programmable output slew-rate control

Software design support and automatic place-and-route provided by

Altera’s development system for Windows-based PCs and Sun

SPARCstation, and HP 9000 Series 700/ 800 workstations

Altera Corporation

123 4 5 6 7...62

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