Datasheet > DSC2233

DSC2233

更新时间： 2023-12-06 20:11:48

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
6页	543K
描述
The DSC2133 and DSC2233 series of programmable, high-performance dual LVDS oscillators utilizes a

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数据手册

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DSC2233 数据手册

Low-Jitter I²C/SPI Programmable Dual LVDS Oscillator

DSC2133 DSC2233

Absolute Maximum Ratings

Ordering Code

Item

Min

Max

Unit Condition

Prog Mode

1: I²C bus

2: SPI bus

Temp Range

E: -20 to 70

I: -40 to 85

Packing

T: Tape & Reel

: Tube

Supply Voltage

-0.3

+4.0

Input Voltage

Junction Temp

Storage Temp

Soldering Temp

-0.3 V_DD+0.3

°C

-55

+150

+260

DSC2 1 33 F I 2

xxxxx

°C

40sec max.

ESD

HBM

Package

F: 3.2x2.5mm

Stability

1: ±50ppm

2: ±25ppm

Freq (MHz)

See Freq. table

4000

400

CDM

1500

Note: 1000+ years of data retention on internal memory

Specifications (Unless specified otherwise: T=25° C)

Parameter

Supply Voltage¹

Condition

Min.

Typ.

Max.

3.6

Unit

V_DD

I_DD

2.25

Supply Current

Supply Current²

EN pin low – outputs are disabled

EN pin high – outputs are enabled

R_L=100Ω, F_O1=F_O2=156.25 MHz

Includes frequency variations due

to initial tolerance, temp. and

power supply voltage

I_DD

±25

±50

Frequency Stability

Aging

Startup Time³

Δf

ppm

Δf

t_SU

1 year @25°C

T=25°C

±5

ppm

Input Logic Levels

Input logic high

Input logic low

V_IH

V_IL

0.75xV_DD

0.25xV_DD

Output Disable Time⁴

Output Enable Time

Pull-Up Resistor²

t_DA

t_EN

Pull-up exists on all digital IO

LVDS Outputs

kΩ

Output Offset Voltage

Delta Offset Voltage

Pk to Pk Output Swing

Output Transition time⁴

Rise Time

R=100Ω Differential

1.125

1.4

Single-Ended

350

200

20% to 80%

R_L=50Ω, C_L= 2pF

t_R

t_F

Fall Time

Frequency

f₀

Single Frequency

Differential

2.3

460

MHz

Output Duty Cycle

Period Jitter⁵

SYM

J_PER

F_O1=F_O2=156.25 MHz

2.5

ps_RMS

200kHz to 20MHz @148.5MHz

100kHz to 20MHz @148.5MHz

12kHz to 20MHz @148.5MHz

0.28

0.4

1.7

Integrated Phase Noise

J_CC

ps_RMS

Notes:

Pin 4 V_DDshould be filtered with 0.01uf capacitor.

Output is enabled if Enable pad is floated or not connected.

t_suis time to 100PPM stable output frequency after V_DDis applied and outputs are enabled.

Output Waveform and Test Circuit figures below define the parameters.

Period Jitter includes crosstalk from adjacent output.

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DSC2133 DSC2233 Page 4 MK-Q-B-P-D-12050109

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