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DS90UH927QSQE

更新时间: 2022-06-07 02:36:30
品牌 Logo 应用领域
德州仪器 - TI 光电二极管
页数 文件大小 规格书
59页 1915K
描述
5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

DS90UH927QSQE 数据手册

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DS90UH927Q  
5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP  
General Description  
Features  
The DS90UH927Q serializer, in conjunction with  
a
Integrated HDCP cipher engine with on-chip key storage  
DS90UH928Q or DS90UH926Q deserializer, provides a so-  
lution for secure distribution of content-protected digital video  
within automotive entertainment systems. This chipset trans-  
lates a FPD-Link video interface into a single-pair high-speed  
serialized interface. The digital video data is protected using  
the industry standard High-Bandwidth Digital Content Protec-  
tion (HDCP) copy protection scheme. The FPD-Link III serial  
bus scheme supports full duplex, high speed forward channel  
data transmission and low-speed back channel communica-  
tion over a single differential link. Consolidation of audio,  
video, and control data over a single differential pair reduces  
the interconnect size and weight, while also eliminating skew  
issues and simplifying system design.  
Bidirectional control channel interface with I2C compatible  
serial control bus  
Low EMI FPD-Link video input  
Supports high definition (720p) digital video format  
5MHz – 85MHz PCLK supported  
RGB888 + VS, HS, DE and I2S audio supported  
Up to 4 I2S Digital Audio inputs for surround sound  
applications  
4 Bidirectional GPIO channels with 2 dedicated pins  
Single 3.3V supply with 1.8V or 3.3V compatible LVCMOS  
I/O interface  
AC-coupled STP Interconnect up to 10 meters  
The DS90UH927Q serializer embeds the clock, content pro-  
tects the data payload, and level shifts the signals to high-  
speed differential signaling. Up to 24 RGB data bits are  
serialized along with three video control signals, and up to four  
I2S data inputs.  
DC-balanced & scrambled Data with Embedded Clock  
Supports HDCP repeater application  
Internal pattern generation  
Low power modes minimize power dissipation  
The FPD-Link data interface allows for easy interfacing with  
data sources while also minimizing EMI and bus width. EMI  
on the high-speed FPD-Link III bus is minimized using low  
voltage differential signaling, data scrambling and random-  
ization, and dc-balancing.  
Automotive grade product: AEC-Q100 Grade 2 qualified  
>8kV HBM and ISO 10605 ESD rating  
Backward compatible modes  
Applications  
The HDCP cipher engine is implemented in both the serializer  
and deserializer. HDCP keys are stored in on-chip memory.  
Automotive Display for Navigation  
Rear Seat Entertainment Systems  
Applications Diagram  
30193027  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
PRODUCTION DATA information is current as of  
publication date. Products conform to specifications per  
the terms of the Texas Instruments standard warranty.  
Production processing does not necessarily include  
testing of all parameters.  
301930 SNLS433A  
Copyright © 1999-2012, Texas Instruments Incorporated  

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