Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS90LV028ATLD/NOPB

DS90LV028ATLD/NOPB

更新时间： 2024-01-25 10:53:04

品牌	Logo	应用领域
德州仪器 - TI		线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数	文件大小	规格书
18页	1146K
描述
DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver

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DS90LV028ATLD/NOPB 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	1.04	差分输出：	NO
输入特性：	DIFFERENTIAL	接口集成电路类型：	LINE RECEIVER
接口标准：	EIA-644; TIA-644	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	1	功能数量：	2
端子数量：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出低电流：	0.002 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
最大接收延迟：	2.5 ns	接收器位数：	2
座面最大高度：	1.75 mm	子类别：	Line Driver or Receivers
最大压摆率：	9 mA	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
电源电压1-最大：	3.6 V	电源电压1-分钟：	3 V
电源电压1-Nom：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3.9 mm
Base Number Matches：	1

DS90LV028ATLD/NOPB 数据手册

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DS90LV028A

www.ti.com

SNLS013E –JUNE 1998–REVISED APRIL 2013

APPLICATION INFORMATION

General application guidelines and hints for LVDS drivers and receivers may be found in the following application

notes: LVDS Owner's Manual (SNLA187), AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165), AN-916

(SNLA219), AN-805 (SNOA233), AN-903 (SNLA034).

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as

is shown in Figure 5. This configuration provides a clean signaling environment for the fast edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair

cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the

range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to

the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a

voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,

but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as

ground shifting, noise margin limits, and total termination loading must be taken into account.

The DS90LV028A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V

common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V.

The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting

may be the result of a ground potential difference between the driver's ground reference and the receiver's

ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters

of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V

(measured from each pin to ground). The device will operate for receiver input voltages up to V_CC, but exceeding

V_CCwill turn on the ESD protection circuitry which will clamp the bus voltages.

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)

0.1μF and 0.01μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the

device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple

vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid

tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply

and ground.

PC BOARD CONSIDERATIONS

Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to

put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side) connectors as possible.

For PC board considerations for the WSON package, please refer to application note AN-1187 “Leadless

Leadframe Package” (SNOA401) It is important to note that to optimize signal integrity (minimize jitter and noise

coupling), the WSON thermal land pad, which is a metal (normally copper) rectangular region located under the

package as seen in Figure 6, should be attached to ground and match the dimensions of the exposed pad on the

PCB (1:1 ratio).

Figure 6. WSON Thermal Land Pad and Pin Pads

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与DS90LV028ATLD/NOPB相关器件

型号	品牌	描述	获取价格	数据表
DS90LV028ATM	TI	DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver	获取价格
DS90LV028ATM	NSC	3V LVDS Dual CMOS Differential Line Receiver	获取价格
DS90LV028ATM/NOPB	TI	DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver	获取价格
DS90LV028ATMX	TI	DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver	获取价格
DS90LV028ATMX/NOPB	TI	DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver	获取价格
DS90LV031	NSC	3V LVDS Quad CMOS Differential Line Driver	获取价格

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