Reꢁ 0; 12/07
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
513/DS4M20
General Description
Features
The DS4M125/DS4M133/DS4M200 are margining clock
oscillators with LVPECL or LVDS outputs. They are
designed to fit in a 5mm x 3.2mm ceramic package with
an AT-cut fundamental-mode crystal to form a complete
clock oscillator. The circuit can generate the following
frequencies and their 5ꢀ frequency deꢁiationsꢂ
125MHz, 133.33MHz, and 200MHz. The DS4M125/
DS4M133/DS4M200 employ a low-jitter PLL to generate
the frequencies. The typical phase jitter is less than
0.9ps RMS from 12kHz to 20MHz.
♦ Frequency Margining: ±±5
♦ Nominal Clock Output Frequencies: 12±MHz,
133.33MHz, and 200MHz
♦ Jitter < 0.9ps RMS from 12kHz to 20MHz
♦ LVPECL or LVDS Output
♦ 3.3V Operating Voltage
♦ Operating Temperature Range: -40°C to +8±°C
♦ Supply Current: < 100mA at 3.3V
♦ Excellent Power-Supply Noise Rejection
♦ ±mm x 3.2mm Ceramic LCCC Package
♦ Output Enable/Disable
Frequency margining is a circuit operation to change
the output frequency to 5ꢀ higher or 5ꢀ lower than the
nominal frequency. Frequency margining is accom-
plished through the margining select pin, MS. This
three-state input pin accepts a three-leꢁel ꢁoltage signal
to control the output frequency. In a low-leꢁel state, the
output frequency is set to the nominal frequency. When
set to a high-leꢁel state, the frequency output is set to
the nominal frequency plus 5ꢀ. When set to the mid-
leꢁel state, the frequency output is equal to the nominal
frequency minus 5ꢀ. If left open, the MS pin is pulled
low by an internal 100kΩ (nominal) pulldown resistor.
The DS4M125/DS4M133/DS4M200 are aꢁailable with
either an LVPECL or LVDS output. The output can be
disabled by pulling the OE pin low. When disabled,
both OUTP and OUTN leꢁels of the LVPECL driꢁer go to
the LVPECL bias ꢁoltage, while the output of the LVDS
driꢁer is a logical one. The OE input is an actiꢁe-high
logic signal and has an internal 100kΩ pullup resistor.
When OE is in a logic-high state, the OUTP and OUTN
outputs are enabled.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
10 LCCC
10 LCCC
10 LCCC
10 LCCC
10 LCCC
10 LCCC
DS4M125P+33
DS4M125D+33
DS4M133P+33
DS4M133D+33
DS4M200P+33
DS4M200D+33
+Denotes a lead(Pb)-free package. The lead finish is JESD97
category e4 (Au oꢁer Ni) and is compatible with both lead-based
and lead-free soldering processes.
The deꢁices operate from a single 3.3V supply ꢁoltage.
Pin Configuration and Selector Guide appear at end of
data sheet.
Applications
Memory Clocks
RAID Systems
Typical Operating Circuit
VCC
OUTP
VCC
OUTP
0.1μF
0.01μF
0.1μF
0.01μF
50Ω
50Ω
DS4M125/
DS4M133/
DS4M200
DS4M125/
DS4M133/
DS4M200
PECL_BIAS AT
- 2.0V
100Ω
MS
OE
MS
OE
V
CC
GND
OUTN
GND
OUTN
LVDS OPTION
LVPECL OPTION
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.