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DS4M133D+33 PDF预览

DS4M133D+33

更新时间: 2024-10-01 06:54:43
品牌 Logo 应用领域
美信 - MAXIM 振荡器时钟
页数 文件大小 规格书
7页 133K
描述
3.3V Margining Clock Oscillator with LVPECL/LVDS Output

DS4M133D+33 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LCC
包装说明:HQCCN,针数:10
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:8.59
JESD-30 代码:R-CQCC-N10长度:5 mm
端子数量:10最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:133.33 MHz
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:HQCCN
封装形状:RECTANGULAR封装形式:CHIP CARRIER, HEAT SINK/SLUG
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:1.62 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:BIPOLAR温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:1 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.2 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

DS4M133D+33 数据手册

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Reꢁ 0; 12/07  
3.3V Margining Clock Oscillator with  
LVPECL/LVDS Output  
513/DS4M20  
General Description  
Features  
The DS4M125/DS4M133/DS4M200 are margining clock  
oscillators with LVPECL or LVDS outputs. They are  
designed to fit in a 5mm x 3.2mm ceramic package with  
an AT-cut fundamental-mode crystal to form a complete  
clock oscillator. The circuit can generate the following  
frequencies and their 5ꢀ frequency deꢁiationsꢂ  
125MHz, 133.33MHz, and 200MHz. The DS4M125/  
DS4M133/DS4M200 employ a low-jitter PLL to generate  
the frequencies. The typical phase jitter is less than  
0.9ps RMS from 12kHz to 20MHz.  
Frequency Margining: ±±5  
Nominal Clock Output Frequencies: 12±MHz,  
133.33MHz, and 200MHz  
Jitter < 0.9ps RMS from 12kHz to 20MHz  
LVPECL or LVDS Output  
3.3V Operating Voltage  
Operating Temperature Range: -40°C to +8±°C  
Supply Current: < 100mA at 3.3V  
Excellent Power-Supply Noise Rejection  
±mm x 3.2mm Ceramic LCCC Package  
Output Enable/Disable  
Frequency margining is a circuit operation to change  
the output frequency to 5ꢀ higher or 5ꢀ lower than the  
nominal frequency. Frequency margining is accom-  
plished through the margining select pin, MS. This  
three-state input pin accepts a three-leꢁel ꢁoltage signal  
to control the output frequency. In a low-leꢁel state, the  
output frequency is set to the nominal frequency. When  
set to a high-leꢁel state, the frequency output is set to  
the nominal frequency plus 5ꢀ. When set to the mid-  
leꢁel state, the frequency output is equal to the nominal  
frequency minus 5ꢀ. If left open, the MS pin is pulled  
low by an internal 100kΩ (nominal) pulldown resistor.  
The DS4M125/DS4M133/DS4M200 are aꢁailable with  
either an LVPECL or LVDS output. The output can be  
disabled by pulling the OE pin low. When disabled,  
both OUTP and OUTN leꢁels of the LVPECL driꢁer go to  
the LVPECL bias ꢁoltage, while the output of the LVDS  
driꢁer is a logical one. The OE input is an actiꢁe-high  
logic signal and has an internal 100kΩ pullup resistor.  
When OE is in a logic-high state, the OUTP and OUTN  
outputs are enabled.  
Ordering Information  
PART  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
10 LCCC  
10 LCCC  
10 LCCC  
10 LCCC  
10 LCCC  
10 LCCC  
DS4M125P+33  
DS4M125D+33  
DS4M133P+33  
DS4M133D+33  
DS4M200P+33  
DS4M200D+33  
+Denotes a lead(Pb)-free package. The lead finish is JESD97  
category e4 (Au oꢁer Ni) and is compatible with both lead-based  
and lead-free soldering processes.  
The deꢁices operate from a single 3.3V supply ꢁoltage.  
Pin Configuration and Selector Guide appear at end of  
data sheet.  
Applications  
Memory Clocks  
RAID Systems  
Typical Operating Circuit  
VCC  
OUTP  
VCC  
OUTP  
0.1μF  
0.01μF  
0.1μF  
0.01μF  
50Ω  
50Ω  
DS4M125/  
DS4M133/  
DS4M200  
DS4M125/  
DS4M133/  
DS4M200  
PECL_BIAS AT  
- 2.0V  
100Ω  
MS  
OE  
MS  
OE  
V
CC  
GND  
OUTN  
GND  
OUTN  
LVDS OPTION  
LVPECL OPTION  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  

DS4M133D+33 替代型号

型号 品牌 替代类型 描述 数据表
DS4M133P+33 MAXIM

完全替代

3.3V Margining Clock Oscillator with LVPECL/LVDS Output
DS4M125D+33 MAXIM

类似代替

3.3V Margining Clock Oscillator with LVPECL/LVDS Output

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